operand address, provided the clock is in the: set,
stopped, or not-set state.
The value of the clock is expressed as an un­
signed, 64-bit fixed-point number. Zeros are stored
for the low-order bit positions that are not provided
by the clock.
When the clock is in the error state, the value
stored is unpredictable. When the clock is in the
not-operational state, zeros are stored at the oper­
and location. The quality of the clock value stored by the in­
struction is indicated by the resultant code
setting.
A serialization function is performed before the
value of the clock is fetched and again after the val­
ue is placed in main storage. CPU operation is de­
layed until all previous accesses by this CPU to main
storage have been completed, as observed by chan­
nels and other CPUs, and then the value of the clock
is No subsequent instructions or their oper­
ands are fetched by this CPU until the clock value
has been placed in main storage, as observcd by
channels and CPUs. Condition Code:
o Clock in set state
1 Clock in not-set state
2 Clock in error state
3 Clock in stopped state or not-operational state
Program Exceptions:
Access (store, operand 2)
Programming Notes
Condition code 0 normally indicates that the clock
has been set by the control program. Accordingly,
the value may be used in elapsed-time measurements
and as a valid time-of -day and calendar indication.
Condition code 1 indicates that the clock's value is
the elapsed time since the power for the cloek was
turned on. In this case the value may be used in
elapsed time measurements but is not a valid time­
of -day indication. Condition codes 2 and 3 mean
that the value provided by STORE CLOCK cannot
be used for time measurement or indication.
Condition code 3 indicates that the clock is either
in the stopped state or not-operational state .. These
two states can normally be distinguished since an
all-zero value is stored when in the not-operational
state.
Bit position 31 of the clock is incremented every
1.048576 seconds; hence, for timing applications involving human responses, the high-order clock
word may provide sufficient resolution.
142 System/370 Principles of Operation To provide compatible operation from one system
to another requires the establishment of a standard
time origin, or epoch, that is, the calendar date and
time to which a clock value of zero corresponds.
January 1, 1900,0 A.M. Greenwich Mean Time is
recommended as the standard epoch for the clock,
although some early support of the TOD clock is not
based on this epoch. A program using the clock's
value as a time-of-day and calendar indication may
have to be aware of the support under which it is
running. With the standard epoch, bit 0 of the TOD clock turns on May 11, 1971 at 11:56:53.685248
A.M. GMT. Therefore, in most cases, the program
can test the high-order bit to determine if the TOD clock value is the standard epoch.
Because of the inaccuracies in setting the clock
value on the basis of a synchronization signal pro­
vided by the operator, the low-order bit positions of
the clock, expressing fractions of seconds, normally
are not valid as indications of time of day. However,
they permit elapsed time measurements of high reso­
lution.
Store Hal/word STH [RX] 40 R1
o 8 12 16 20 31
The contents of bit positions 16-31 of the general
register designated by the Rl field are placed un­
changed at the second-operand location. The second
operand is two bytes in length.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Store Multiple STM [RS] 90 o 8 12 16 20 31
The set of general registers starting with the register
specified by Rl and ending with the register speci­
fied by R3 is stored at the locations designated by
the second-operand address.

The storage area where the contents of the gener­
al registers are placed starts at the location designat­
ed by the second-operand address and continues
through as many locations as needed. The general
registers are stored in the ascending order of their
addresses, starting with the register specified by Rl
and continuing up to and including the register speci­
fied by R3, with register 0 following register 15.
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (store, operand 2)
Subtract
SR [RR]
o 8 12 15
S [RX]
58
o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the difference is placed in the first-
operand location.
Subtraction is considered to be performed by
adding the one's complement of the second operand
and a low-order one to the first operand. All 32 bits
of both operands participate, as in ADD. If the carry
out of the sign-bit position and the carry out of the
high-order numeric bit position agree, the difference
is if they disagree, an overflow occurs.
The overflow causes a program interruption when
the fixed-point overflow mask bit is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero 3 Overflow
Program Exceptions:
Access (fetch, operand 2 of S only)
Fixed-Point Overflow
Programming Note
The use of the one's complement and the low-order
one instead of the two's complement of the second
operand is necessary for proper recognition of over­
flow when subtracting the maximum negative num­
ber.
When, in the RR format, the Rl and R2 fields
designate the same register, subtracting is equivalent
to clearing the register.
Subtracting a maximum negative number from
another maximum negative number gives a zero re­
sult and no overflow.
Subtract Hal/word
SH [RX]
48
l
o 8 12 16 20 31
The second operand is subtracted from the first oper­
and, and the difference is placed in the first-operand
location. The second operand is two bytes in length
and is considered to be a 16-bit signed integer.
The second operand is expanded to 32 bits before
the subtraction by propagating the sign-bit value
through the 16 high-order bit positions.
Subtraction is considered to be performed by
adding the one's complement of the expanded sec­
ond operand and a low-order one to the first oper­
and. All 32 bits of both operands participate, as in
ADD. If the carry out of the sign-bit position and
the carry out of the high-order numeric bit position
agree, the difference is if they disagree,
an overflow occurs. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Difference is zero
1 Difference is less than zero
2 Difference is greater than zero
3 Overflow
Program Exceptions:
Access (fetch, operand 2)
Fixed-Point Overflow
Subtract Logical
SLR [RR]
1F
o 8 12 15
SL
o 8 12 16 20 31
General Instructions 143