ject to monitoring by the prefixing mechanism are
referred to as "real" addresses. When prefixing is
not installed, a real address and the corresponding
absolute address are identical.
When dynamic address translation is invoked,
addresses specified by the program are normally
translated to real addresses before main storage is
accessed. The address specified by the program is
referred to as a logical address. When dynamic ad­
dress translation is not invoked, a logical address and
the corresponding real address are identical.
All CPUs and channels having access to a com­
mon main-storage location have access to the entire 2,048-byte block containing that location and the
associated key in storage. All CPU s and channels
refer to a shared main-storage location by using the
same absolute address.
Available storage is normally assigned to contigu­
ous absolute addresses starting at address 0, and is
always assigned in multiples of 2,048 bytes. An ex­
ception condition is recognized when an attempt is
made to access main storage by using an absolute
address that does not correspond to a tion. Normally, the exception condition is recognized
only when the information associated with the abso­
lute address is actually required and not when the
operation can be completed without using the in­
formation.
In/ormation Positioning
Integral Boundaries
Certain units of information must be located in main
storage on an integral boundary. A boundary is
called integral for a unit of information when its
storage address is a mUltiple of the length of the unit
in bytes. For example, a word (four bytes) is on an
integral boundary when it is located in storage so
that its address is a multiple of the number 4. A half­
word (two bytes) is on an integral boundary when it
has an address that is a multiple of the number 2,
and a doubleword (eight bytes) is on an integral
boundary when it has an address that is a mUltiple of
the number 8.
When storage addresses designate half words,
words, and doublewords on integral boundaries, the
binary representation of the address contains one,
two, or three low-order zero bits, respectively.
Instructions must appear on halfword integral
boundaries, and channel command words and the
operands of certain privileged instructions must ap­
pear on integral boundaries. • t + I I I bf!f Jk + I I I kf;:!'! ; f Integral Boundaries for Halfwords, Words, and Doublewords
Byte-Oriented-Operand Feature
The byte-oriented-operand feature is standard on
System/370. This feature permits storage operands
of most unprivileged operations to appear on any
byte boundary.
The feature does not pertain to instruction ad­
dresses, or to the operands for COMPARE AND SWAP (CS) and COMPARE DOUBLE AND SW AP (CDS). Instructions must appear on even
byte boundaries. The low-order bit of a branch ad­
dress must be zero, and the instruction EXECUTE
must designate the subject instruction at an even
byte address. COMP ARE AND SWAP must desig­
nate a word boundary, and COMPARE DOUBLE AND SW AP must designate a doubleword bounda­
ry. Significant performance degradation is possible
when storage operands are not positioned at ad­
dresses that are integral multiples of the operand
length. To ensure optimum performance, storage
operands should be aligned on integral boundaries,
and the use of unaligned operands should be re­
served for exceptional cases.
Central Processing Unit The central processing unit (CPU) is the controlling
center of the system. It contains the sequencing and
processing controls for instruction execution, inter­
ruption action, timing facilities, initial program load- System Organization 15

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
ing, and other system-related functions.
The: physical makeup of the CPU controls in the
various models of the System/370 may be different,
but the logical function remains the same. The result
of executing a valid instruction is the same for each
modeL Tht: CPU, in executing instructions, can process
binary integers and floating-point numbers of fixed
length, decimal integers of variable length, and logi­
cal information of either fixed or variable length. Processing may be in parallel or in series; the width
of the processing elements, the multiplicity of the
shifting paths, and the degree of simultaneity in per­
forming the different types of arithmetic differ from
one CPU to another without affecting the logical
results.
Instructions which the CPU executes fall into five
classes: system-control, general, decimal, floating­
point, and input/output instructions. The system­
control and input/output instructions are privileged
instructions that can be executed only when the CPU is in the supervisor state. The general instruc­
tions are used in performing fixed-point, logical,
branching, and other control and data-manipulation
operations. The decimal instructions operate on data
in the decimal format, and the floating-point instruc­
tions on data in the floating-point format.
To perform its functions, the CPU uses a certain
amount of internal storage other than main storage.
Portions of this storage can be designated. by the
program, such as the current program status word (PS\\T), the general registers, the floating-point reg­
isters, the control registers, the prefix register, and
registers associated with the timing facilities.
The current PSW contains information used to
control instruction sequencing and to hold and indi­
cate the states of the system in relation to the pro­
gram currently being executed. Registers associated
with the timing facilities contaJn the time-of-day
clock:, the clock comparator, and the CPU timer. The
genelral, floating-point, and control registers are dis­ cussed separately in the following paragraphs. The
instruction operation code determines which type of
register is to be used in an operation.
General Registers
The CPU can address information in 16 general
registers. The general registers can be used as base­
address registers and index registers in address arith­
metic and as accumulators in general arithmetic and logical operations. Each register contains 32 bits. The gene:ral registers are identified by the numbers 0-15 16 System/370 Principles of Operation
and are designated by a four-bit R field in an instruc­
tion (see accompanying illustration). Some instruc­
tions provide for addressing multiple general registers
by having several R fields.
For some operations, two adjacent general regis­
ters are coupled together, providing a 64-bit format.
In these operations, the program must designate an
even-numbered register, which contains the high­
order bits. The next higher numbered register con­
tains the low-order bits.
In addition to their use as accumulators in general
arithmetic and logical operations, 15 of the 16 gen­
eral registers are also used as base-address and index
registers in address generation. In these cases, the
registers are designated by a four-bit B field or X
field in an instruction. A value of zero in the X or B
field specifies no index or base is to be applied, and,
thus, general register 0 cannot be designated as con­
taining an index or base address.
Floating-Point Registers
Four floating-point registers are available for
floating-point operations. They are identified by the
numbers 0, 2, 4, and 6 (see illustration). Each
floating-point register contains 64 bits and can con­
tain either a short (32-bit) or a long (64-bit) floating­
point operand. A short operand occupies the high­
order bit positions of a floating-point register. The
low-order portion of the register is ignored and re­
mains unchanged in arithmetic calling for short ope­
rands. Two pairs of adjacent floating-point registers
can be used for extended operands: registers 0, 2,
and registers 4,6. Each of these pairs provides a 128-
bit format.
Control Registers
The CPU can designate 16 control registers, each 32
bit positions in length. The bit positions in the regis­
ters are assigned to particular facilities in the system,
such as program-event recording, and are used either
to specify whether an operation can take place or to
provide special information required by the facility. On any particular model, only those bit positions are
necessarily provided which are required by the in­
stalled facilities.
The control registers are identified by the num­
bers 0-15 and are designated by a four-bit R field in
the instructions LOAD CONTROL and STORE CONTROL. Multiple control registers can be ad­
dressed by these instructions.