Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22·0498 izing the intennediate quotient is never necessary,
but a right-shift of one digit position may be called
for. The intennediate-quotient characteristic is ad­
justed for the shift. The intennediate-quotient frac­
tion is subsequently truncated to the proper result­
fraction length.
The sign of the quotient is determined by the
rules of algebra, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-overflow exception is recognized
when the final-quotient characteristic exceeds 127
and the fraction is not zero. The operation is com­
pleted, and a program interruption occurs. The result
is normalized, the sign and fraction remain correct,
and the characteristic is 128 less than the correct
value.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent­
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under­
flow mask bit is zero, a program interruption does
not take place; instead, the operation is completed
by making the quotient a true zero.
Exponent underflow is not signaled when an op­
erand characteristic becomes less than zero during
prenonnalization or the intennediate-quotient char­
acteristic is less than zero, but the final quotient can
be expressed without encountering exponent under­
flow.
A floating-point divide exception is recognized
when the divisor fraction is zero. The operation is
suppressed, and a program interruption for floating­
point divide occurs.
When the dividend fraction is zero, the quotient is
made a true zero, and a possible exponent overflow
or exponent underflow is not recognized. A division
of zero by zero, however, causes the operation to be suppressed and an interruption for floating-point
divide to occur. The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized. Cond.rtion Code:
The code remains unchanged. PrognfJm Exceptiom: Operation (if the floating-point feature is not
installed) Aceess (fetch, operand 2 of DD and DE only) Specification Exponent Overflow
164 System/370 Principles of Operation Exponent Underflow
Floating-Point Divide
Halve
HER Rl,R2
[RR, Short Operands]
34
o 8 12 15
HDR Rl,R2
[RR, Long Operands]
24
o 8 12 15
The second operand is divided by 2, and the normal­
ized quotient is placed in the first-operand location.
The fraction of the second operand is shifted right
one bit position, placing the contents of the low­
order bit position· into the high-order bit position of
the guard digit and introducing a zero into the high­
order bit position of the fraction. The intennediate
result is subsequently normalized, and the normal­
ized quotient is placed in the first-operand location.
The guard digit participates in the normalization.
The sign of the quotient is the same as that of the
second operand, unless the quotient is made a true
zero, in which case the sign is made plus.
An exponent-underflow exception exists when the
characteristic of the nonnalized quotient is less than
zero and the fraction is not zero. If the exponent­
underflow mask bit is one, a program interruption
occurs. The result is nonnalized, its sign and fraction
remain correct, and the characteristic is made 128
larger than the correct value. If the exponent under­
flow mask bit is zero, program interruption does not
take place; instead, the operation is completed by
making the quotient a true zero.
When the fraction of the second operand is zero,
the result is made a true zero, and no exceptions are
recognized.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Specification
Exponent Underflow

Programming Notes
With short and long operands, the halve operation is
identical to a divide operation with the number 2 as
divisor. Similarly, the result of HDR is identical to
that of MD or MDR with one-half as a multiplier.
No multiply operation corresponds to HER, since no
multiply operation produces short results.
The result of HALVE is replaced by a true zero
only when the second-operand fraction is zero, or
when exponent underflow occurs with the exponent­
underflow mask set to zero. When the fraction of the
second operand is zero, except for the low-order bit
position, the low-order one is shifted into the guard
digit position and participates in the postnormaliza­
tion.
Load
LER Rl,R2
[RR, Short Operands]
38
o 8 12 15
LE Rl,D2(X2,B2)
[RX, Short Operands]
78 I R, I X21 8
2 I D2 I 0 8 12 16 20 31
LDR Rl,R2
[RR, Long Operands]
28 I R, I R2 I 0 8 12 15
LD R 1 ,D2(X2,B2)
[RX, Long Operands] I 68 I R,I x 2 I 8
2 D2 0 8 12 16 20 31
The second operand is placed unchanged in the first­
operand location.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Condition Code:
The code remains unchanged.
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of LE and LD only)
Specification
Load and Test
LTER Rl,R2
[RR, Short Operands]
o 8 12 15
LTDR R 1,R2
[RR, Long Operands]
22
o 8 12 15
The second operand is placed unchanged in the first­
operand location, and its sign and magnitude are
tested to determine the setting of the condition code.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception isrecog­
nized.
ResUlting Condition Code: ° Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Specification
Programming Note
When the same register is specified as the first­
operand and second-operand location, the operation
is equivalent to a test without data movement.
Load Complement
LeER R 1,R2
[RR, Short Operands]
33
o 8 12 15
Floating-Point Instructions 165