underflow mask bit is one, the operation is complet­
ed by making the characteristic 128 larger than the
correct value. The result is normalized, and the sign
and fraction remain correct. A program interruption
for exponent underflow then takes place. When ex­
ponent underflow occurs and the exponent­
underflow mask bit is zero, a program interruption
does not take place; instead, the operation is com­
pleted by making the result a true zero. For AXR,
exponent underflow is not recognized when the low­
order characteristic is less than zero, but the high­
order characteristic is zero or above.
A significance exception exists when the
intermediate-sum fraction, including the guard digit,
is zero. If the significance mask bit is one, the
intermediate-sum characteristic remains unchanged
and becomes the characteristic of the ,result. No nor­
malization occurs, and a program interruption for
significance takes place. If the significance mask bit
is zero, the program interruption does not occur;
instead, the result is made a true zero.
The Rl field for AER, AE, ADR, and AD" and
the R2 field for AER and ADR must designate regis­
ter 0,2,4, or 6. The Rl and R2 fields for AXR must
designate register 0 or 4.
Otherwise, a specification
exception is recognized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -
Program Exceptions: Operation (if the floating-point feature is not
installed, or, for AXR, if the extended­ preeision floating-point feature is not installed)
Access (fetch, operand 2 of AE and AD only) Specification Exponent Overflow
Exponent Underflow
Significance
Programming Note
Interchanging the two operands in a floating-point
addition does not affect the value of the sum.
162 System/370 Principles of Operation Add Unnormalized AUR Rl,R2
[RR, Short Operands]
o 8 12 15 AU [RX, Short Operands]
7E
o 8 12 16 20 AWR Rl,R2
[RR, Long Operands]
o 8 12 15
AW Rl,D2(X2,B2)
[RX, Long Operands]
6E I R, I x
2 I 8
2 D2 0 8 12 16 20 The second operand is added to the first operand,
and the unnormalized sum is placed in the first­
operand location.
31
31
The execution of ADD UNNORMALIZED is
identical to that of ADD NORMALIZED, except
that, after the addition, the intermediate-sum frac­
tion is truncated to the proper result-fraction length
without performing normalization. Leading zeros are
not eliminated in the result fraction, exponent under­
flow cannot occur, and the guard digit does not par­
ticipate in the recognition of significance exception.
A significance exception is recognized when the
intermediate-sum fraction, not including the guard
digit, is zero.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
Resulting Condition Code:
o Result fraction is zero
1 Result is less than zero
2 Result is greater than zero
3 -

Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of AU and AW only)
Specification
Exponent Overflow
Significance
Compare
CER Rl,R2
[RR, Short Operands]
o 8 12 15
CE Rl,D2(X2,B2)
[RX, Short Operands]
Resulting Condition Code:
o Operands are equal
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Operation (if the floating-point feature is not
installed)
Access (fetch, operand 2 of CE and CD only)
Specification
Programming Note
Numbers with zero fractions compare equal even
when they differ in sign or characteristic.
Divide
DER Rl,R2
79 I R, I X
2 I B2 D2 I [RR, Short Operands 1 [ 3D I R, I R, CDR Rl,R2
[RR, Long Operands]
29
o 8 12 15
CD Rl,D2(X2,B2)
[RX, Long Operands]
o 8 12 15
DE Rl,D2(X2,B2)
[RX, Short Operands]
7D
o 8 12 16 20 31
DDR Rl,R2 I 69 I R, I x
2 I B2 D2 I [RR, Long Operands 1 I 2D I R, I R2
The first operand is compared with the second op­
erand, and the condition code is set to indicate the
result.
Comparison is algebraic, taking into account the
sign, fraction, and exponent of each number. An
equality is established by following the rules for nor­
malized floating-point subtraction. When the inter­
mediate sum, including the guard digit, is zero, the
operands are equal. An exponent inequality is not
decisive for magnitude determination since the frac­
tions may have different numbers of leading zeros.
Neither operand is changed as a result of the opera­
tion.
An exponent-overflow, exponent-underflow, or
significance exception cannot occur.
The Rl and R2 fields must designate register 0, 2,
4, or 6; otherwise, a specification exception is recog­
nized.
o 8 12 15"
DD Rl,D2(X2,B2)
[RX, Long Operands]
6D
o 8 12 16 20 The first operand (the dividend) is divided by the
second operand (the divisor) and replaced by the
normalized quotient. No remainder is preserved.
31
Floating-point division consists in characteristic
subtraction and fraction division. The operands are
prenormalized, and the difference between the divi­
dend and divisor characteristics of the normalized
operands, plus 64, is used as the characteristic of the
intermediate quotient.
All dividend and divisor fraction digits participate
in forming the fraction of the quotient. Postnormal-
Floating-Point Instructions 163