imply storage logical validity, or that the fields stored
as a result of the machine-check interruption are
valid. The presence and extent of the system re­
covery capability depend on the model.
Timer Damage (ID): Bit 3, when one, indicates
that damage has occurred to the interval timer or to
location 80. Timing Facility Damage (CD): Bit 4, when one,
indicates that damage has occurred to either the
time-of-day clock, the CPU timer, or the clock com­
parator. The timing-facility-damage machine-check
condition is set whenever any of the following oc­
curs:
1. The time-of-day clock enters the not­
operational state.
2. The time-of -day clock enters the error state.
3. The time-of-day clock is not in the error state,
and the STORE CLOCK instruction encoun­
ters an error which results in setting condition
code 2. This condition also sets instruction
processing damage.
4.
The CPU timer is in error, and the CPU is ena­
bled for CPU-timer interruptions. On some
models, this condition may be recognized even
when the CPU is not enabled for CPU-timer interruptions.
5. The CPU timer is in error, and STORE CPU TIMER is executed. This condition also sets
instruction processing damage.
6. The clock comparator is in error, and the CPU is enabled for clock-comparator interruptions. On some models, this condition may be recog­
nized even when the CPU is not enabled for
clock-comparator interruptions.
7. The clock comparator is in error, and STORE CLOCK COMPARATOR is executed. This
condition also sets instruction processing dam­
age. External Damage (ED): Bit 5, when one, indicates
that damage has occurred to a channel, channel con­
troller, switching unit, or other unit external to the CPU, or to a storage unit during operations not di­
rectly associated with the CPU. Channel-detected
malfunctions are reported as external damage only
when the channel is unable to report the malfunction
by using the 110 interruption. Depending on the
model and on the type and extent of the error, an
external damage condition may be indicated as sys­
tem damage instead of external damage.
Degradation (DG): Bit 7, when one, indicates that
continuous degradation of system performance,
more serious than that indicated by system recovery,
has occurred. Degradation may be reported when
system-recovery conditions exceed a machine pre­
established threshold or when unit deletion has oc­
curred. The presence and extent of the degradation­
report capability depends on the model.
Warning (W): Bit 8, when one, indicates that dam­
age is imminent in some part of the system (for ex­
ample, that power is about to fail, or that a loss of
cooling is occurring). Whether warning conditions
are recognized depends on the model.
Time of Interruption Occurrence
Bits 14 and 15 of the machine-check interruption
code indicate when the interruption occurred in rela­
tion to the error.
Backed Up (B): Bit 14, when one, indicates that
the point of interruption is at a hardware checkpoint
before the point of error. This bit is meaningful only
when instruction processing damage is also set to
one. The presence and extent of the capability to
indicate a backed-up condition depends on the mod­
el.
Programming Note
The backed-up situation is reported as instruction­
processing damage rather than system recovery be­
cause the malfunction has not been circumvented
and damage would have occurred if instruction pro­ cessing had continued.
Delayed (D): Bit 15, when one, indicates that some
or all of the machine-check conditions were delayed
in being reported because the CPU was disabled for
that type of interruption at the time the error was
detected.
Storage Error Type
Bits 16-18 of the machine-check interruption code
are used to indicate invalid CBC or near-valid CBC
detected in main storage or invalid CBC in a key in
storage. The failing-storage address field, when indi­
cated as valid, identifies an address within the stor­
age checking block or within the 2,048-byte block
associated with the key in storage. The portion of
the system affected by an invalid CBC is indicated in
the subclass field of the machine-check interruption
code. I/O-detected storage errors, when indicated as 110 interruptions, may not result in a machine-check
interruption or may be reported as system recovery.
CBC errors in storage or in the key in storage that
Machine-Check Handling 179

are detected on prefetched or unused data mayor
may not be reported, depending on the model. Storage Errol' (SE): Bit 16, when one,
indicates that a checking block in main storage con­
tains invalid CBC. Storage Errol' COn'ected (SC): Bit 17, when one,
indicates that a checking block in main storage con­
tained near·valid cac and that the data portion of
the information has been corrected before being
used by the CPU or channel. Depending on the
model, the contents of the checking block in main
storage mayor may not have been restored to valid
CBC. The presence and extent of the storage-error­
correction capability depends on the model.
Key in Storage /Jrror Uncorrected (KE): Bit 18,
when one, indicates that a key in storage contains
invalid eBC.
Programming Note
The storage·error-type bits do not in themselves
indicate the occurrence of damage because the error
detected may not have affected the result. The sub­
class bits indicate, in conjunction with the storage­
error-type bits, the area affected by the storage er­
ror. Interruption Code Validity Bits
Bits 20-31 <and bits 46 and 47 of the machine-check
interruption code are validity bits. Each bit indicates
the validity of a particular field in main storage.
With the exception of the storage logical validity bit
(bit 31), each bit is associated with a field stored
during the machine .. check interruption. When a va­
lidity bit is one, it indicates that this specific field is
valid with respect to the indicated point of interrup­
tion and that no error was detected when the data
was stored. When the bit is zero, one or more of the
following conditions may have occurred: the original
informatilon was incorrect, the original information
had invalid CSC, additional malfunctions were de­
tected during the s.toring of the information, or none
or only part of the information waS stored. Even
though the information is unpredictable, the machine
will attempt, when to ensure that the in­
formatioltl in storage has valid CBC and thus reduce
the possibility of additional machine checks being
caused. PSW EMWP Volldily (WP): Bit 20, when one,
indicates that bits 12-15 of the machine-check old PSW are correct. I HO System/370 Principles of Op.eration PSW Masks and Key Validity (MS): Bit 21, when
one, indicates that all PSW bits other than the inter­
ruption code, ILC, EMWP, instruction address, con­
dition code, and program mask of the machine-check
old PSW are correct. Program Mask and Condition Code Validity
(PM): Bit 22, when one, indicates that the program
mask and condition code in the machine-check old PSW are correct.
Imtruction Address Validity (1A): Bit 23, when one,
indicates that the instruction address in the old PSW is correct.
Failing-Storage Address Valid (FA): Bit 24, when
one, indicates that a correct failing-storage address
has been stored. The presence and extent of the
capability to indicate the failing-storage address de­
pend on the model. When no storage errors are re­
ported, that is, bits 16-18 of the machine-check in­
terruption code are zeros, the failing-storage address
is meaningless, even though it may be indicated as
valid.
Region Code Valid (RC): Bit 25, when one, indi­
cates that a correct region code has been stored. The
presence of the region code depends on the model.
Floating-Point Registers Valid (FP): Bit 27, when
one, indicates that the contents of the floating-point
register save area reflect the correct state of the
floating-point registers at the point of interruption.
When the floating-point feature is not installed, this
bit is set to zero.
General Registers Valid (GR): Bit 28, when one,
indicates that the contents stored in the general reg­
ister save area reflect the correct state of the general
registers at the point of interruption.
Control Registers Valid (CR): Bit 29, when one,
indicates that the contents stored in the control reg­
ister save area reflect the correct state of the control
registers at the point of interruption.
Logout Valid (LG): Bit 30, when one, indicates
that the CPU extended logout information was cor­
rectly stored. Storage Logical Validity (ST): Bit 31, when one,
indicates that the contents of those storage locations
which are modified by the instruction processing
stream contain the correct information relative to the
point of interruption. That is, all stores prior to the