point of interruption are completed, and all stores, if
any, beyond the point of interruption are suppressed.
When a store prior to the point of interruption is
suppressed because of an invalid CBC, the storage
logical validity bit may be indicated as one, provided
that the invalid CBC is preserved as invalid.
CPU Timer Valid: Bit 46, when one, indicates that
theCPU timer is not in error and that the contents
stored in theCPU-timer save area (location 216)
reflect the correct state of theCPU timer at the time
the interruption occurred.
Clock Comparator Valid: Bit 47, when one, indi
cates that the clock comparator is not in error and
that the contents stored in the clock-comparator
save area (location 224) reflect the correct state of
the clock comparator.
Programming Note
The validity bits must be used in addition to the sub
class indication and time-of -occurrence bits in order
to determine the extent of the damage caused by the
machine-check condition. The fourPSW validity
bits, the three register validity bits, the two timing
facility validity bits, and the storage logical validity
bit must all be ones in addition to one of the follow
ing in order to indicate that no damage has yetoc, curred to the system: • All of the damage subclass bits (0, 1,3,4,5)
are zeros.• Instruction processing damage is the only dam
age subclass.bit which is one, the backed-up bit
is one, and the delayed bit is zero.
Machine-Check Extended Logout Length
Bits 48-63 of the machine-check interruption code
contain a 16-bit binary value indicating the length in
bytes of the information most recently stored in the
extended logout area, starting at the location speci-
fied by the machine-check extended logout pointer.
When no extended logout has occurred, this field is
set to zero.
Programming Note
When asynchronous machine-check extended log
outs are permitted (control register 14, bit 8 is one),
more than one extended logout may have occurred.
The length stored on interruption doesnot necessari
ly indicate the longest logout which has occurred.
Machine-Check Control Registers
Control Register 14
o 3
R DEW A
M M M M L
4I : 10 Control register 14 contains mask bits that specify
whether certain conditions can cause machine-check
interruptions and control bits that determine when a
logout may occur. With the exception of bit0, which
is provided on all models, each of the bits is neces
sarily provided only if the associated function is pro
vided.
Check-Stop Control
The check-stop control bit (CS), which is bit° of
control register 14, controls the system action taken
when an exigent machine-check condition occurs
under one of the following two'conditions:
1. When theCPU is disabled for machine-check
interruptions (that is,PSW bit 13 is zero).
2. When a second exigent machine-check condi
tion occurs during the process of storing the
machine-check interruptioncode, storing the machine-check old PSW, or fetching the
machine-check newPSW during a machine
check interruption.
If the check-stop control bit is one and either
condition occurs, the machine the check-stop if the check-stop control bit is zeto, the ma
chine may attempt to corttinue ormay enter the
check-stop state, depending on the type of error and
the model. The check -stop control bit is initialized to
one. If damage occurs to control register 14, the
check-stop control bit is assumed to be one.
Logout Controls
Synchronous Machine-CheckExtended Logout Con
trol (SL): Bit 1 of control register 14 controls the
logout action during a machine-check interruption. If
the bit is one, the machine-check extended logout
area may be changed during the interruption; if the
bit is zero, the area may bechungedonly under con
trol of the asynchronous machine-check extended
logout control bit (bit 8 of control register 14). Bit 1
of control register 14 is initialized to one.
Machine-Checkl-landling 181
any, beyond the point of interruption are suppressed.
When a store prior to the point of interruption is
suppressed because of an invalid CBC, the storage
logical validity bit may be indicated as one, provided
that the invalid CBC is preserved as invalid.
CPU Timer Valid: Bit 46, when one, indicates that
the
stored in the
reflect the correct state of the
the interruption occurred.
Clock Comparator Valid: Bit 47, when one, indi
cates that the clock comparator is not in error and
that the contents stored in the clock-comparator
save area (location 224) reflect the correct state of
the clock comparator.
Programming Note
The validity bits must be used in addition to the sub
class indication and time-of -occurrence bits in order
to determine the extent of the damage caused by the
machine-check condition. The four
bits, the three register validity bits, the two timing
facility validity bits, and the storage logical validity
bit must all be ones in addition to one of the follow
ing in order to indicate that no damage has yet
are zeros.
age subclass.bit which is one, the backed-up bit
is one, and the delayed bit is zero.
Machine-Check Extended Logout Length
Bits 48-63 of the machine-check interruption code
contain a 16-bit binary value indicating the length in
bytes of the information most recently stored in the
extended logout area, starting at the location speci-
fied by the machine-check extended logout pointer.
When no extended logout has occurred, this field is
set to zero.
Programming Note
When asynchronous machine-check extended log
outs are permitted (control register 14, bit 8 is one),
more than one extended logout may have occurred.
The length stored on interruption does
ly indicate the longest logout which has occurred.
Machine-Check Control Registers
Control Register 14
o 3
R DEW A
M M M M L
4
whether certain conditions can cause machine-check
interruptions and control bits that determine when a
logout may occur. With the exception of bit
is provided on all models, each of the bits is neces
sarily provided only if the associated function is pro
vided.
Check-Stop Control
The check-stop control bit (CS), which is bit
control register 14, controls the system action taken
when an exigent machine-check condition occurs
under one of the following two'conditions:
1. When the
interruptions (that is,
2. When a second exigent machine-check condi
tion occurs during the process of storing the
machine-check interruption
machine-check new
check interruption.
If the check-stop control bit is one and either
condition occurs, the machine
chine may attempt to corttinue or
check-stop state, depending on the type of error and
the model. The check -stop control bit is initialized to
one. If damage occurs to control register 14, the
check-stop control bit is assumed to be one.
Logout Controls
Synchronous Machine-Check
trol (SL): Bit 1 of control register 14 controls the
logout action during a machine-check interruption. If
the bit is one, the machine-check extended logout
area may be changed during the interruption; if the
bit is zero, the area may be
trol of the asynchronous machine-check extended
logout control bit (bit 8 of control register 14). Bit 1
of control register 14 is initialized to one.
Machine-Check