point of interruption are completed, and all stores, if
any, beyond the point of interruption are suppressed.
When a store prior to the point of interruption is
suppressed because of an invalid CBC, the storage
logical validity bit may be indicated as one, provided
that the invalid CBC is preserved as invalid.
CPU Timer Valid: Bit 46, when one, indicates that
the CPU timer is not in error and that the contents
stored in the CPU-timer save area (location 216)
reflect the correct state of the CPU timer at the time
the interruption occurred.
Clock Comparator Valid: Bit 47, when one, indi­
cates that the clock comparator is not in error and
that the contents stored in the clock-comparator
save area (location 224) reflect the correct state of
the clock comparator.
Programming Note
The validity bits must be used in addition to the sub­
class indication and time-of -occurrence bits in order
to determine the extent of the damage caused by the
machine-check condition. The four PSW validity
bits, the three register validity bits, the two timing
facility validity bits, and the storage logical validity
bit must all be ones in addition to one of the follow­
ing in order to indicate that no damage has yet oc,­ curred to the system: All of the damage subclass bits (0, 1,3,4,5)
are zeros. Instruction processing damage is the only dam­
age subclass.bit which is one, the backed-up bit
is one, and the delayed bit is zero.
Machine-Check Extended Logout Length
Bits 48-63 of the machine-check interruption code
contain a 16-bit binary value indicating the length in
bytes of the information most recently stored in the
extended logout area, starting at the location speci-
fied by the machine-check extended logout pointer.
When no extended logout has occurred, this field is
set to zero.
Programming Note
When asynchronous machine-check extended log­
outs are permitted (control register 14, bit 8 is one),
more than one extended logout may have occurred.
The length stored on interruption does not necessari­
ly indicate the longest logout which has occurred.
Machine-Check Control Registers
Control Register 14
o 3
R DEW A
M M M M L
4 I : 10 Control register 14 contains mask bits that specify
whether certain conditions can cause machine-check
interruptions and control bits that determine when a
logout may occur. With the exception of bit 0, which
is provided on all models, each of the bits is neces­
sarily provided only if the associated function is pro­
vided.
Check-Stop Control
The check-stop control bit (CS), which is bit ° of
control register 14, controls the system action taken
when an exigent machine-check condition occurs
under one of the following two'conditions:
1. When the CPU is disabled for machine-check
interruptions (that is, PSW bit 13 is zero).
2. When a second exigent machine-check condi­
tion occurs during the process of storing the
machine-check interruption code, storing the machine-check old PSW, or fetching the
machine-check new PSW during a machine­
check interruption.
If the check-stop control bit is one and either
condition occurs, the machine the check-stop if the check-stop control bit is zeto, the ma­
chine may attempt to corttinue or may enter the
check-stop state, depending on the type of error and
the model. The check -stop control bit is initialized to
one. If damage occurs to control register 14, the
check-stop control bit is assumed to be one.
Logout Controls
Synchronous Machine-Check Extended Logout Con­
trol (SL): Bit 1 of control register 14 controls the
logout action during a machine-check interruption. If
the bit is one, the machine-check extended logout
area may be changed during the interruption; if the
bit is zero, the area may be chungedonly under con­
trol of the asynchronous machine-check extended
logout control bit (bit 8 of control register 14). Bit 1
of control register 14 is initialized to one.
Machine-Check l-landling 181
Input I O,'tput Extended Logout Control (lL): Bit 2
of contrOiI register 14, when one, permits channel
logout into the 110 extended logout area as part of
an 110 interruption. When the 110 extended logout
mask is zero, 1/0 extended logouts cannot occur.
This bit is initialized to zero.
Asynchronous Machine-Check Extended Logout
Control (AL): Bit 8 of control register 14, in con­
junction with PSW bit 13, controls asynchronous
change of the machine-check extended logout area.
When this bit and PSW bit 13 are both ones, the
machine may change the machine-check extended
logout area at any time. This bit is initialized to zero.
Asynchronous Fixed Logout Control (FL): Bit 9 of
control register 14, when one, permits the fixed log­
out area to be changed at any time. When this bit is
zero, the fixed logout area may be changed only
during a machine-check interruption or during an 110 interruption. This bit is initialized to zero.
Programming Notes
The maximum logout information is obtained by
setting both the synchronous and asynchronous
machine-check extended logout control bits to ones.
Both of these bits must be zeros to prevent any
changes to the machine-check extended logout area.
When asynchronous machine-check extended logout
is allowed, use of the machine-check extended log­
out area may produce unpredictable results.
When the asynchronous fixed logout control bit is
one, program use of the fixed logout area should be
restricted to the fetching of data from this are,a.
Store operations or channel programs reading into
the fixed logout area may cause machine checks or
undetected errors if the store occurs during CPU retry. Note that this is an exception to the rule
that programming errors do not cause machine­
check indications.
Machine··Check Subclass Masks
Bits 4-7 of control register 14, in conjunction with PSW bit 13, control various machine-check subclass
conditions. When PSW bit 13 is one and the subclass
mask is OIne, the associated condition initiates a
machine-,check interruption. If the subclass mask is
zero, the associated condition does not initiate an
182 System/370 Principles of Operation
interruption, but the condition may be presented
with another condition which initiates the interrup­
tion. All conditions presented are then cleared. Recovery Report Mask (RM): Bit 4 of control reg­
ister 14 controls recovery-interruption conditions.
This bit is initialized to zero.
Degradation Report Mask (DM): Bit 5 of control
register 14 controls degradation-interruption condi­
tions. This bit is initialized to zero.
External Damage Report Mask (EM): Bit 6 of con­
trol register 14 controls the following machine-check­
interruption conditions: timer damage, timing facility
damage, and external damage. This bit is initialized
to one.
Warning Mask (WM): Bit 7 of control register 14
controls all warning conditions. This bit is initialized
to zero.
Control Register 15
o 8
Machine-Check Extended Logout
Address
29 31
Bits 8-28 of control register 15, with three low-order
zeros appended, specify the starting location of the
machine-check extended logout area. The contents
of control register 15 are initialized by setting bit 22
to one and ali other bits to zeros, which specifies a
starting address of 512 (decimal). The machine­
check extended logout address is a real address.
When a model provides machine-check extended
logout, control register 15 is implemented.
Programming Note
The availability and extent of the machine-check
extended logout area differs among models and, for
any particular model, may depend on the features or
engineering changes installed. In order to provide for
such variations, the program should determine the
extent of the logout by means of STORE CPU ID
whenever a storage area for the extended logout is to
be assigned. A length of zero in the MCEL field
indicates that no MCEL is provided.
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