Control). See also "Input/Output Device Address-
. " mg.
If the addressed device is not installed or has been
logically removed from the control unit, but the as­
sociated control unit is operational and the address
has been assigned to the control unit (for example,
access mechanism 7 on the IBM 3830 Storage Con­
trol that has only access mechanisms 0-3 installed)
the device is said to be not-ready. When an instruc­
tion is addressed to a device in the not-ready state,
the control unit responds to the selection and indi­
cates unit-check whenever the not-ready state pre­
cludes a successful execution of the operation. See "Unit Check. " Inte"uption Pending in Subchannel (AIX): The
addressed channel is available. An interruption con­
dition is pending in the addressed subchannel be­
cause of the concluding of the portion of the opera­
tion involving the use of channel facilities. The sub­
channel is in a position to provide information for a
complete CSW. The interruption condition can indi­
cate concluding of an operation at the addressed I/O device or at another device on the subchannel. The
state of the addressed device is not significant, ex­
cept when TEST I/O is addressed to the device as­
sociated with the concluded operation, in which case
the CSW contains status information provided by
the device. The state AIX does not occur on the selector
channel. On the selector channel, the existence of an
interruption condition in the sub channel immediately
causes the channel to assign to this condition the
highest priority for I/O interruptions and, hence,
leads to tlhe state IIX.
Subchannel Working (A WX): The addressed chan­
nel is available. The addressed subchannel is execut­
ing a previously initiated operation or chain of oper­
ations and has not yet received the channel end for
the last operation. The state of the addressed device
is not significant, except when HALT I/O or HALT
DEVICE is issued. During HALT I/O and HALT
DEVICE, the state of the device may be interrogat­
ed and will then be indicated in either the CSW or
the condition code.
The subchannel-working state does not occur on
the selector channel since all operations on the selec­
tor channel are executed in the burst mode and
cause the channel to be in the working state
(WWX).
194 System/370 Principles of Operation Subchannel Not Operational (ANX): The addressed
channel is available. The addressed sub channel on
the multiplexer channel is not operational. A sub­
channel is not operational when it is not provided in
the system. This state cannot occur on the selector
channel.
Interruption Pending in Channel (IXX): The ad­
dressed channel is not working and has established
which device will cause the next I/O interruption
from this channel. The state where the channel con­
tains a pending interruption condition is distin­
guished only by the instruction TEST CHANNEL.
This instruction does not cause the sub channel and I/O device to be interrogated. The other I/O in­
structions, with the exception of STORE CHAN­
NEL ID, consider the channel available when it con­
tains a pending interruption condition. A channel
with a pending interruption condition may be con­
sidered to be working by the instruction STORE CHANNEL ID. When the channel assigns priority
for interruptions among devices, the interruption
condition is preserved in the I/O device or subchan­
nel. (See "Interruption Conditions. ") Channel Working (WXX): The addressed channel
is operating in the burst mode. In the case of the
multiplexer channel, a burst of bytes is currently
being handled. In the case of the selector channel, an
operation or a chain of operations is currently being
executed, and the channel end for the last operation
has not yet been reached. The states of the ad­
dressed device and, in the case of the multiplexer
channel, of the subchannel are not significant. De­
pending on the channel type and system model,
TEST I/O and HALT DEVICE may consider the
channel to be available when the channel is working
with a device other than the addressed device.
Channel Not Operational (NXX): The addressed
channel is not operational. A channel is not opera­
tional when it is not provided in the system, when
power is off in the channel, or when it is not config­
ured to the CPU. The states of the addressed I/O device and sub channel are not significant.
Resetting of the Input/Output System
Two types of resetting can occur in the I/O system:
an I/O system reset and an I/O selective reset. The
response of each type of I/O device to the two kinds
of reset is specified in the SL and SRL publications
for the device.

I/O System Reset
The I/O system reset is performed when the CPU to
which the channel is configured performs a program
reset, initial-program reset, system-clear reset, or
power-on reset, when a power-on sequence is per­
formed by the channel, and, under certain condi­
tions, when a channel detects equipment malfunc­
tions. I/O system reset causes the channel to conclude
operations on all subchannels. Status information
and all interruption conditions in all subchannels are
reset, and all operational subchannels are placed in
the available state. The channel signals system reset
to all I/O devices attached to it. I/O Selective Reset
The I/O selective reset is performed by some chan­
nels when they detect certain equipment malfunc­
tions. I/O selective reset causes the channel to signal
selective reset to the device that is connected to the
channel at the time the malfunction is detected. No
subchannels are reset.
Effect of Reset on a Working Device
If the device is currently communicating over the I/O interface, the device immediately disconnects
from the channel. Data transfer and any operation
using the facilities of the control unit are immediate­
ly concluded, and the I/O device is not necessarily
positioned at the beginning of a block. Mechanical
motion not involving the use of the control unit,
such as rewinding magnetic tape or positioning a
disk-access mechanism, proceeds to the normal
stopping point, if possible. The device appears in the
working state until the termination of mechanical
motion or the inherent cycle of operation, if any,
whereupon it becomes available. Status information
in the device and control unit is reset, but an inter­
ruption condition may be generated upon completing
any mechanical operation.
Reset Upon Malfunction
The type of reset executed in the channel depends
on the type of malfunction and the channel. When a
reset occurs upon malfunction, the program is alert­
ed by an interruption or, when the malfunction is
detected during the execution of an I/O instruction,
by the setting of the condition code. In either case
the CSW identifies the condition. The device ad­
dressed by the I/O instruction is not necessarily the
device that is reset. In channels sharing equipment
with the CPU, malfunctioning detected by the chan­
nel may be indicated by a machine-check interrup­
tion, which mayor may not be followed by an I/O interruption. When no I/O interruption takes place,
a CSW is not stored, and a device is not identified.
The method of identifying malfunctions depends on
the model.
Condition Code
The results of certain tests by the channel and de­
vice, and the original state of the addressed part of
the I/O system are used during the execution of an I/O instruction to set one of four condition codes in
the PSW. The condition code is set at the time the
execution of the instruction is concluded, that is, the
time the CPU is released to proceed with the next
instruction. The condition code ordinarily indicates
whether or not the channel has performed the in­
struction and, if not, the reason for the rejection. In
the case of START I/O FAST RELEASE executed
independently of the device, a condition code 0 may
be set that is later superseded by a deferred condi­
tion code stored in the CSW. Branch-on-condition
operations following an operation that sets the con­
dition code use the code for decision-making.
The following table lists the conditions identified
and the corresponding condition codes for each I/O instruction. The states of the I/O system and associ­
ated abbreviations were previously defined in "States of the Input/ Output System." The digits in
the table represent the decimal value of the code.
The instructions START I/O and START I/O FAST RELEASE can set code 0 or 1 for the AAA
state, depending on the type of operation initiated.
Equipment malfunctions and programming errors
generally cause condition code 1 to be set and the CSW to be stored.
The available condition is indicated only when no
errors are detected during the execution of the I/O instruction.
When a subchannel on the multiplexer channel
contains a pending interruption condition (state
AIX), the I/O device associated with the concluded
operation normally is in the interruption-pending
state. When the channel detects during the execu­
tion of TEST I/O that the device is not operational,
condition code 3 is set. Similarly, condition code 3 is
set when HALT I/O or HALT DEVICE is ad­
dressed to a sub channel in the working state (state
AWX), but the device turns out to be not operation­
al.
Error conditions, including all equipment or pro­
gramming errors detected by the channel or the I/O device during execution of the I/O instruction, gen­
erally cause the CSW to be stored. On some models,
however, a channel equipment error may cause a
machine-check interruption but no I/O interruption
to occur, with no storing of the CSW. Three types of Input/Output Operations 195