Conditions 1/0 Available AAA Interruption pending in device AAI Device working AAW
Device not operational AAN Interruption pending in subchannel AIX For the addressed device
For another device Subchannel working AWX
With the addressed device
With another device Subchannel not operational ANX Interruption pending in channel IXX Channel working WXX
With the addressed device
With another device
Channel not operational NXX
Explanation:
The entries in this column indicate the condition-code
setting when the CLRIO function is executed.
* Whenever condition code 1 is set, the CSW or its status
portion is stored at location 64 during execution of the
instruction.
** When CLEAR I/O encounters the WXX state, either
condition code 2 is set, or the channel is treated as available and the condition code is set according to the
state of the subchannel. When the channel is treated as available, the condition codes for the WXX states am the
same as for the AXX states.
***A condition code 1 (with the CSW stored) or 2 may be
set, dep1ending on the channel. of The condition code depends on the state of the subchannel, the channel type, and the system model. If the sub­ channel is not operational, a condition code 2 or 3 is set. If the subchannel is available or working with the addreSSE!d device, a condition code 2 is set. Otherwise, a
condition code 0 or 2 is set.
# When a "device not operational" response is received in selectin!J the addressed device, condition code 3 is set.
@ START 1/0 FAST RELEASE may cause the same
condition code to be set as for START 1/0 or may cause
conditicln code 0 to be set.
Condition-Code Settings for I/O States and Instructions
errors can occur:
Channel Equipment Error: The channel can detect
the following equipment errors during execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, and HALT DE­
VICE:
1. The device address that the channel received
on the interface during il1itial selection either
has a parity error or is not the same as the one
196 Syst 1 em/370 Principles of Operation Condition Code Settings SIO SIOF TIO CLRI01 HIO HDV TCH STIOC O,1*@ 0 0 1* 1* 0 0 1*@ 1* 0 1 * 1 * 0 0 1*@ 1* 0 1* 1 * 0 0 3@ 3 0 3 3 0 0 2
2
2
2
3
2
2
3
1* 1* 0 0 0 0 2 0 0 0 0 0 2 1* 1*# 1*# 0 0 2 0 1*# 0 0 0 3 3 3 3 0 0 See Note ##
2 *** 2 + 2 ##
2. 2 of 2 ##
3 3 3 3 3 3
+ The condition code depends on the 1/0 interface sequence, the channel type, and the system model. If the channel ascertains
that the device received the signal to terminate, a condition code
1 is set and the CSW stored. Otherwise, a condition code 2 is
set.
## When the channel is unable to store the channel I D
because of
the working or interruption pending state, a condition code 2
is set. If the working or interruption pending state does not
preclude storing the channel 10, a condition code 0 is set. • If the subchannel is interruption pending for the addressed
device, condition code 1 may be set depending on the channel type.
Note: For the purpose of executing START I/O, START I/O FAST RELEASE, TEST 1/0, CLEAR 1/0, HALT DEVICE, and
HALT I/O, a channel containing a pending interruption condition
appears the same as an available channel, and the condition-code
setting depends on the states of the subchannel and device. The
condition codes for the I XX states are the same as for the AXX
states, where the Xs represent the states of the subchannel and the
device. As an example, the condition code for the lAW state is
the same as for AAW.
the channel sent out. Some device other than
the one addressed may be malfunctioning.
2. The unit-status byte that the channel received
on the interface during initial selection has a
parity error.
3. A signal from the I/O device occurred at an
invalid time or had invalid duration.
4. The channel detected an error in its control
equipment. (This is also true for STORE CHANNEL ID and TEST CHANNEL.)

The channel may perform an I/O selective reset
or an 1/ ° system reset or may generate a halt signal,
depending on the type of error and the model. If a CSW is stored, channel control check or interface
control check is indicated, depending on the type of
error.
Channel Programming Error: The channel can de­
tect the following programming errors during execu­
tion of START I/O or START I/O FAST RE­ LEASE. All of the error conditions are indicated
during START 1/ 0, and during START 1/ ° FAST RELEASE when it is executed as START I/O, by
the condition-code setting and by the status portion
of the CSW. When the SIOF function is performed,
the first two error conditions are indicated as for START I/O, and the remaining conditions are indi­
cated in a subsequent interruption.
1. Invalid CCW address specification in CAW.
2. Invalid CAW format.
3. Invalid CCW address in CAW.
4.
First-CCW location protected against fetching.
5. First CCW specifies transfer in channel.
6. Invalid command code in first CCW.
7. Invalid count in first CCW.
8. Invalid format for first CCW.
9. If channel indirect data addressing (CIDA) was
specified, an invalid data address specification
in the first CCW. 10. If CIDA was specified, an invalid data address
in the first CCW.
11. If CIDA was specified, the first-IDAW loca­
tion protected against fetching.
12. If CIDA was specified, invalid format for the
first IDAW.
The CSW indicates program check, except for
items 4 and 11, for which protection check is indi­
cated.
Device Error: Programming or equipment errors
detected by the device during the execution of START I/O, or START I/O FAST RELEASE are
indicated by unit check or unit exception in the CSW. The conditions responsible for unit check and unit
exception for each type of I/O device are detailed in
the SL or SRL publication for the device.
Instruction Formats
All I/O instructions use the following S format: Op Code
o 16 20 31
Except for STORE CHANNEL ID, bit positions
8-14 of these instructions are ignored. Bit position
15 is ignored by the instruction TEST CHANNEL
but is decoded as part of the operation code for START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, and HALT DE­ VICE. The second-operand address specified by the B2
and D2 fields is not used to designate data, but in­
stead is used to identify the channel and 1/ ° device.
Address computation follows the rules of address
arithmetic. The address has the following format:
Device
Address 17/////////////. .Channel = Address Bit positions 0-7 are not part of the address. Bit
positions 8-15, which constitute the high-order por­
tion of the three-byte address, are ignored. Bit posi­
tions 16-23 of the sum contain the channel address
while bit positions 24-31 identify the device on the'
channel and, additionally in the case of the multi­
plexer channel, the sub channel.
All 1/ ° instructions cause a serialization function
to be performed. CPU operation is delayed until all
previous CPU accesses to main storage have been
completed, as observed by channels and other CPUs, and then the addressed channel is selected.
No subsequent instructions or their operands are
accessed until the execution of the 1/ ° instruction
has been completed.
Note: In the detailed descriptions of the individual
instructions, the mnemonic and the symbolic oper­
and designation for the IBM System/370 assembly
language are shown with each instruction. In the
case of START I/O, for example, SIO is the mne­
monic and D2(B2) the operand designation.
List of Instructions
The mnemonics, format, and operation codes of the I/O instructions follow. The table also indicates that
all 1/ ° instructions cause a program interruption
when they are encountered in the problem state, and
that all 1/ ° instructions set the condition code.
Programming Note
The instructions START I/O, START I/O FAST RELEASE,TESTI/O,CLEARI/O,HALTI/O, HALT DEVICE, and STORE CHANNEL ID·cause
a CSW to be stored. To prevent the contents of the CSW stored by the instruction from being destroyed
by an immediately following I/O interruption, the CPU must be disabled for all I/O interruptions be­
fore START I/O, START I/O FAST RELEASE,
Input/Output Operations 197