I/O System Reset
The I/O system reset is performed when the CPU to
which the channel is configured performs a program
reset, initial-program reset, system-clear reset, or
power-on reset, when a power-on sequence is per­
formed by the channel, and, under certain condi­
tions, when a channel detects equipment malfunc­
tions. I/O system reset causes the channel to conclude
operations on all subchannels. Status information
and all interruption conditions in all subchannels are
reset, and all operational subchannels are placed in
the available state. The channel signals system reset
to all I/O devices attached to it. I/O Selective Reset
The I/O selective reset is performed by some chan­
nels when they detect certain equipment malfunc­
tions. I/O selective reset causes the channel to signal
selective reset to the device that is connected to the
channel at the time the malfunction is detected. No
subchannels are reset.
Effect of Reset on a Working Device
If the device is currently communicating over the I/O interface, the device immediately disconnects
from the channel. Data transfer and any operation
using the facilities of the control unit are immediate­
ly concluded, and the I/O device is not necessarily
positioned at the beginning of a block. Mechanical
motion not involving the use of the control unit,
such as rewinding magnetic tape or positioning a
disk-access mechanism, proceeds to the normal
stopping point, if possible. The device appears in the
working state until the termination of mechanical
motion or the inherent cycle of operation, if any,
whereupon it becomes available. Status information
in the device and control unit is reset, but an inter­
ruption condition may be generated upon completing
any mechanical operation.
Reset Upon Malfunction
The type of reset executed in the channel depends
on the type of malfunction and the channel. When a
reset occurs upon malfunction, the program is alert­
ed by an interruption or, when the malfunction is
detected during the execution of an I/O instruction,
by the setting of the condition code. In either case
the CSW identifies the condition. The device ad­
dressed by the I/O instruction is not necessarily the
device that is reset. In channels sharing equipment
with the CPU, malfunctioning detected by the chan­
nel may be indicated by a machine-check interrup­
tion, which mayor may not be followed by an I/O interruption. When no I/O interruption takes place,
a CSW is not stored, and a device is not identified.
The method of identifying malfunctions depends on
the model.
Condition Code
The results of certain tests by the channel and de­
vice, and the original state of the addressed part of
the I/O system are used during the execution of an I/O instruction to set one of four condition codes in
the PSW. The condition code is set at the time the
execution of the instruction is concluded, that is, the
time the CPU is released to proceed with the next
instruction. The condition code ordinarily indicates
whether or not the channel has performed the in­
struction and, if not, the reason for the rejection. In
the case of START I/O FAST RELEASE executed
independently of the device, a condition code 0 may
be set that is later superseded by a deferred condi­
tion code stored in the CSW. Branch-on-condition
operations following an operation that sets the con­
dition code use the code for decision-making.
The following table lists the conditions identified
and the corresponding condition codes for each I/O instruction. The states of the I/O system and associ­
ated abbreviations were previously defined in "States of the Input/ Output System." The digits in
the table represent the decimal value of the code.
The instructions START I/O and START I/O FAST RELEASE can set code 0 or 1 for the AAA
state, depending on the type of operation initiated.
Equipment malfunctions and programming errors
generally cause condition code 1 to be set and the CSW to be stored.
The available condition is indicated only when no
errors are detected during the execution of the I/O instruction.
When a subchannel on the multiplexer channel
contains a pending interruption condition (state
AIX), the I/O device associated with the concluded
operation normally is in the interruption-pending
state. When the channel detects during the execu­
tion of TEST I/O that the device is not operational,
condition code 3 is set. Similarly, condition code 3 is
set when HALT I/O or HALT DEVICE is ad­
dressed to a sub channel in the working state (state
AWX), but the device turns out to be not operation­
al.
Error conditions, including all equipment or pro­
gramming errors detected by the channel or the I/O device during execution of the I/O instruction, gen­
erally cause the CSW to be stored. On some models,
however, a channel equipment error may cause a
machine-check interruption but no I/O interruption
to occur, with no storing of the CSW. Three types of Input/Output Operations 195
Conditions 1/0 Available AAA Interruption pending in device AAI Device working AAW
Device not operational AAN Interruption pending in subchannel AIX For the addressed device
For another device Subchannel working AWX
With the addressed device
With another device Subchannel not operational ANX Interruption pending in channel IXX Channel working WXX
With the addressed device
With another device
Channel not operational NXX
Explanation:
The entries in this column indicate the condition-code
setting when the CLRIO function is executed.
* Whenever condition code 1 is set, the CSW or its status
portion is stored at location 64 during execution of the
instruction.
** When CLEAR I/O encounters the WXX state, either
condition code 2 is set, or the channel is treated as available and the condition code is set according to the
state of the subchannel. When the channel is treated as available, the condition codes for the WXX states am the
same as for the AXX states.
***A condition code 1 (with the CSW stored) or 2 may be
set, dep1ending on the channel. of The condition code depends on the state of the subchannel, the channel type, and the system model. If the sub­ channel is not operational, a condition code 2 or 3 is set. If the subchannel is available or working with the addreSSE!d device, a condition code 2 is set. Otherwise, a
condition code 0 or 2 is set.
# When a "device not operational" response is received in selectin!J the addressed device, condition code 3 is set.
@ START 1/0 FAST RELEASE may cause the same
condition code to be set as for START 1/0 or may cause
conditicln code 0 to be set.
Condition-Code Settings for I/O States and Instructions
errors can occur:
Channel Equipment Error: The channel can detect
the following equipment errors during execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, and HALT DE­
VICE:
1. The device address that the channel received
on the interface during il1itial selection either
has a parity error or is not the same as the one
196 Syst 1 em/370 Principles of Operation Condition Code Settings SIO SIOF TIO CLRI01 HIO HDV TCH STIOC O,1*@ 0 0 1* 1* 0 0 1*@ 1* 0 1 * 1 * 0 0 1*@ 1* 0 1* 1 * 0 0 3@ 3 0 3 3 0 0 2
2
2
2
3
2
2
3
1* 1* 0 0 0 0 2 0 0 0 0 0 2 1* 1*# 1*# 0 0 2 0 1*# 0 0 0 3 3 3 3 0 0 See Note ##
2 *** 2 + 2 ##
2. 2 of 2 ##
3 3 3 3 3 3
+ The condition code depends on the 1/0 interface sequence, the channel type, and the system model. If the channel ascertains
that the device received the signal to terminate, a condition code
1 is set and the CSW stored. Otherwise, a condition code 2 is
set.
## When the channel is unable to store the channel I D
because of
the working or interruption pending state, a condition code 2
is set. If the working or interruption pending state does not
preclude storing the channel 10, a condition code 0 is set. If the subchannel is interruption pending for the addressed
device, condition code 1 may be set depending on the channel type.
Note: For the purpose of executing START I/O, START I/O FAST RELEASE, TEST 1/0, CLEAR 1/0, HALT DEVICE, and
HALT I/O, a channel containing a pending interruption condition
appears the same as an available channel, and the condition-code
setting depends on the states of the subchannel and device. The
condition codes for the I XX states are the same as for the AXX
states, where the Xs represent the states of the subchannel and the
device. As an example, the condition code for the lAW state is
the same as for AAW.
the channel sent out. Some device other than
the one addressed may be malfunctioning.
2. The unit-status byte that the channel received
on the interface during initial selection has a
parity error.
3. A signal from the I/O device occurred at an
invalid time or had invalid duration.
4. The channel detected an error in its control
equipment. (This is also true for STORE CHANNEL ID and TEST CHANNEL.)
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