The channel may perform an I/O selective reset
or an 1/ ° system reset or may generate a halt signal,
depending on the type of error and the model. If a CSW is stored, channel control check or interface
control check is indicated, depending on the type of
error.
Channel Programming Error: The channel can de­
tect the following programming errors during execu­
tion of START I/O or START I/O FAST RE­ LEASE. All of the error conditions are indicated
during START 1/ 0, and during START 1/ ° FAST RELEASE when it is executed as START I/O, by
the condition-code setting and by the status portion
of the CSW. When the SIOF function is performed,
the first two error conditions are indicated as for START I/O, and the remaining conditions are indi­
cated in a subsequent interruption.
1. Invalid CCW address specification in CAW.
2. Invalid CAW format.
3. Invalid CCW address in CAW.
4.
First-CCW location protected against fetching.
5. First CCW specifies transfer in channel.
6. Invalid command code in first CCW.
7. Invalid count in first CCW.
8. Invalid format for first CCW.
9. If channel indirect data addressing (CIDA) was
specified, an invalid data address specification
in the first CCW. 10. If CIDA was specified, an invalid data address
in the first CCW.
11. If CIDA was specified, the first-IDAW loca­
tion protected against fetching.
12. If CIDA was specified, invalid format for the
first IDAW.
The CSW indicates program check, except for
items 4 and 11, for which protection check is indi­
cated.
Device Error: Programming or equipment errors
detected by the device during the execution of START I/O, or START I/O FAST RELEASE are
indicated by unit check or unit exception in the CSW. The conditions responsible for unit check and unit
exception for each type of I/O device are detailed in
the SL or SRL publication for the device.
Instruction Formats
All I/O instructions use the following S format: Op Code
o 16 20 31
Except for STORE CHANNEL ID, bit positions
8-14 of these instructions are ignored. Bit position
15 is ignored by the instruction TEST CHANNEL
but is decoded as part of the operation code for START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, and HALT DE­ VICE. The second-operand address specified by the B2
and D2 fields is not used to designate data, but in­
stead is used to identify the channel and 1/ ° device.
Address computation follows the rules of address
arithmetic. The address has the following format:
Device
Address 17/////////////. .Channel = Address Bit positions 0-7 are not part of the address. Bit
positions 8-15, which constitute the high-order por­
tion of the three-byte address, are ignored. Bit posi­
tions 16-23 of the sum contain the channel address
while bit positions 24-31 identify the device on the'
channel and, additionally in the case of the multi­
plexer channel, the sub channel.
All 1/ ° instructions cause a serialization function
to be performed. CPU operation is delayed until all
previous CPU accesses to main storage have been
completed, as observed by channels and other CPUs, and then the addressed channel is selected.
No subsequent instructions or their operands are
accessed until the execution of the 1/ ° instruction
has been completed.
Note: In the detailed descriptions of the individual
instructions, the mnemonic and the symbolic oper­
and designation for the IBM System/370 assembly
language are shown with each instruction. In the
case of START I/O, for example, SIO is the mne­
monic and D2(B2) the operand designation.
List of Instructions
The mnemonics, format, and operation codes of the I/O instructions follow. The table also indicates that
all 1/ ° instructions cause a program interruption
when they are encountered in the problem state, and
that all 1/ ° instructions set the condition code.
Programming Note
The instructions START I/O, START I/O FAST RELEASE,TESTI/O,CLEARI/O,HALTI/O, HALT DEVICE, and STORE CHANNEL ID·cause
a CSW to be stored. To prevent the contents of the CSW stored by the instruction from being destroyed
by an immediately following I/O interruption, the CPU must be disabled for all I/O interruptions be­
fore START I/O, START I/O FAST RELEASE,
Input/Output Operations 197

TEST I/O, CLEAR I/O, HALT I/O, HALT DE­
VICE, and STORE CHANNEL ID are issued and
must remain disabled until the information in the
CSW provided by the instruction has been acted
upon or stored elsewhere for later use.
Clear l/O CLRIO [S] C 9DOl I B2 I D2 I o Either a TIO or CLRIO function is performed, de­
pending on the channel and the block-multiplexing
control: control register 0, bit 0. The TIO function is
performed when the CLRIO function is not imple­
mented by the channel or when the block­
multiplexing control bit is zero.
The TIO function is described in the definition of
the instruction TEST I/O. Bits 8··14 of the instruction are ignored. Bit posi­
tions 16-31 of the second-operand address identify
the channel, subchannel, and I/O device to which
the instruction applies.
The CLRIO function causes the current operation
with the addressed device to be discontinued and the
state of the operation at the time of the discontinua­
tion to be indicated in the stored CSW.
When the subchannel is available, interruption
pending with another device, or working with anoth­
er device, no channel action is taken, and condition
code ° is set. Channels not capable of determining
subchannel states while in the working state may
instead set condition code 2.
When the subchannel is either working with the
addressed device or in the interruption-pending state
with the addressed device, the CLRIO function
causes the channel to discontinue the operation with
the addressed device by storing the status of the
operation in the CSW and making the subchannel
available. When the channel is working with the
addressed device, the instruction causes the device to
be signaled to terminate the current operation. Some
channels may, instead, indicate busy and cause no
channel action.
When any of the following conditions occurs, the
CLRIO function causes the CSW at location 64 to
be stored. The contents of the entire CSW pertain to
the I/O device addressed by the instruction.
1. The channel is in the available or interruption­
pending state, and the subchannel contains an
interruption-pending condition for the ad­
dressed device or is working with the addressed
device. The protection-key, command-address,
and count fields describe the state of the opera­
tion at the time of the execution of the instruc­
tion.
2. The channel is working with the addressed
device. The protection-key, command-address,
and count fields describe the state of the opera­
tion at the time the instruction is executed.
(Some channels alternatively indicate busy un­
der this condition.)
3. The channel is working with a device other
than the one addressed, and the subchannel
contains an interruption-pending condition for l\lame Mnemonic Characteristics Code CLEAR I/O HALT DEVICE HALT I/O START I/O START I/O FAST RELEASE STORE CHANNEL ID TEST CHANNEL TEST I/O Explanation: C Condition code is set.
M Privilegl3d-operation exception. S S instruction format. CLRIO HDV HIO SIO SIOF STIDC TCH TIO Bits 8-14 of the operation code are ignored. + Bits 8-15 of the operation code are ignored.
Input/Output-Instruction Summary
198 System/370 Principles of Operation S C M 9001* S C M 9E01* S C M 9EOO* S C M 9COO* S C M 9C01 * S C M B203 S C M 9FOO+ S C M 9000*