• Channel available interruption (CAl) • A programming error associated with the CCW
or first IDA W following the SIOF function
The interruption conditions from the channel,
except for CAl, can be accompanied by other chan­
nel status indications, but none of the device status
bits is on when the channel initiates the interruption.
The channel available interruption (CAl) condi­
tion is provided on all block-multiplexer channels
and causes the entire CSW to be replaced by a new
set of bits. All fields of the CSW are set to zero.
The I/O address stored in the I/O old PSW in BC
mode and in the I/O communications area in EC
mode contains a zero device address and a channel
address identifying the interrupting channel.
The channel generates the CAl condition only if
it previously had responded with a condition code 2
to an I/O instruction other than HALT I/O or
HALT DEVICE and if the busy condition thus indi­
cated no longer exists. When the busy condition
which caused condition code 2 was due to a subchan­
nel busy with a device other than the one addressed,
the concluding of the busy condition is not signaled
by a CAl. Since any other interruption condition
(except PCI) accomplishes the same function as
CAl, a pending CAl condition is reset upon the oc­
currence of any interruption (except PCI) on that
channel. Some channels also reset a pending CAl
condition when another interruption condition
(except PCI) is cleared by a TEST I/O on the same
channel. The occurrence of another channel-busy
condition prior to the CAl causes the CAl condition
to be suspended until the busy condition is past.
Programming Note
The CAl is designed to inform the program that a
channel which previously indicated busy is no longer
busy. The CAl condition pending in a channel does
not cause the rejection of a subsequent START I/O or START I/O FAST RELEASE but does cause a
condition code 1 to be returned to TEST CHAN­
NEL. The CAl can therefore be used as a tool for
keeping I/O requests in sequence by using it in con­
junction with TEST CHANNEL. A channel which
responded with condition code 2 because of a chan­
nel busy condition does not subsequently respond
with a condition code 0 to a TEST CHANNEL with­
out clearing an interruption condition in the interim.
Priority of Interruptions
All requests for I/O interruption are asynchronous
to the activity in the CPU, and interruption condi­
tions associated with more than one I/O device can
exist at the same time. The priority among requests Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
is controlled by two types of mechanisms--one es­ the priority among interruption conditions
associated with devices attached to the same chan­
nel, and another establishes priority among requests
from different channels. A channel requests an I/O interruption only after it has established priority
among requests from its devices. The conditions
responsible for the requests are preserved in the
devices or channels until accepted by the CPU. Assignment of priority to requests for interruption
associated with devices on anyone channel is a
function of the type of channel, the type of interrup­
tion condition, and the position of the device on the I/O interface. A device's position on the interface is
not related to its The selector channel assigns the highest priority
to conditions associated with the portion of the op­
eration in which the channel is involved. These con­
ditions include channel end, program-controlled­
interruption, HALT I/O or HALT DEVICE in the
channel, and errors prematurely concluding a chain
of operations. The selector channel cannot handle
any interruption conditions other than those due to the PCI flag while operation is in progress.
As soon as the selector channel has cleared the
interruption conditions associated with data transfer
it starts monitoring devices for attention, control­
unit-end, and device-end conditions and for the chan­
nel-end condition associated with operations con­
cluded by HALT I/O, HALT DEVICE, or CLEAR I/O. The highest priority is assigned to the I/O device that first identifies itself on the interface. On the byte-multiplexer channel the priority
among requests for interruption is based on response
from devices. The highest priority is assigned to the
device that first identifies itself with an interruption
condition or that requests service for data transfer
and contains the PCI condition in the subchannel.
The assignment of priority among interruption
conditions for a block-multiplexer channel differs
among models. Some block-multiplexer channels
assign priorities as done by the byte-multiplexer
channel. Others assign priorities in a manner which
appears random.
Except for conditions associated with concluding
of data transfer, the current assignment of priority
for interruption among devices on a channel may be
canceled when START I/O, START I/O FAST RELEASE,.TEST I/O, CLEAR I/O, HALT I/O, or HALT DEVICE is issued to the channel. When­
ever the assignment is canceled, the channel resumes
monitoring for interruption conditions and reassigns
the priority on completion of the activity associated
with the I/O instruction.
Input/Output Operations 227

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
The assignment of priority among requests for
interruption from channels is based on the type of
channel and its address assignment. The priorities of
channels 1-15 are in the order of their addresses,
with channel 1 having the highest priority. The inter­
ruption priority of multiplexer channel 0 is not fixed,
and depends on the model and on the current activi­
ty in the channel. Its priority may be above, below,
or between those of channels 1-15.
Intenuption Action
An I/O interruption can occur only when the chan­
nel the device is not masked and
after the execution of the current instruction in the CPU has been finished. If a channel has established
the priority among requests for interruption from
devices while the CPU was disabled for interruptions
from the channel, the interruption occurs immediate­
ly after the finishing of the instruction removing the
mask and before the next instruction is executed.
This interruption is associated with the highest prior­
ity condition on the channel. If interruptions are
allowed from more than one channel concurrently,
the interruption occurs from the channel having the
highest priority among those requesting interruption.
If the priority among interruption conditions has
not yet been established in the channel by the time
the interruption is allowed, the interruption does not
necessarily occur immediately after the finishing of
the instruction removing the mask. This delay can
occur regardless of how long the interruption condi­
tion has existed in the device or the subchannel.
The interruption causes the current program sta­
tus word (PSW) to be stored as the old PSW at loca­
tion 56 and causes the CSW associated with the intenuption to be stored at location 64. Subsequent­
ly, a new PSW is loaded from location 120, and
processing resumes in the state indicated by this PSW. The I/O device or, in the case of control-unit
end, the control unit causing the interruption is iden­
tified in BC mode by the channel address in bit posi­
tions 16-23 and by the device address in bit posi­
tions 24-31 of the old PSW. In EC mode, the I/O device or control unit is identified in the I/O-address field (locations 186-187) of the I/O communica­
tions area (IOCA). The CSW associated with the
interruption identifies the condition responsible for
the interruption and provides further details about
the progress of the operation and the status of the device. ProgJramming Note
When a number of I/O devices on a shared control
unit are concurrently executing operations such as
rewinding tape or positioning a disk-access mecha-
228 Systern/370 Principles of Operation nism, the initial device-end signals generated on
completion of the operations are provided in the
order of generation, unless command chaining is
specified for the operation last initiated. In the latter
case, the control unit provides the device-end signal
for the last initiated operation first, and the other
signals are delayed until the subchannel is freed.
Whenever interruptions due to the device-end signals
are delayed either because the channel is masked
or the subchannel is busy, the original order of
the signals is destroyed.
Channel Status Word
The channel status word (CSW) provides to the
program the status of an I/O device or the indica­
tion of the conditions under which an I/O operation
has been concluded. The CSW is formed, or parts of it-are replaced, in the process of I/O interruptions
and possibly during execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, HALT DEVICE, and STORE CHANNEL ID. The CSW is placed in main storage
at reallocation 64 of the CPU to which the channel
is configured, and is available to the program at this
location until the time the next I/O interruption
occurs or until another I/O instruction causes its
contents to be replaced, whichever occurs first.
When the CSW is stored as a result of an I/O interruption, the I/O device is identified in BC mode
in the interruption code of the old PSW and in EC
mode in the I/O-address field of the I/O communi­
cations area (IOCA). The information placed in the CSW by START I/O, START I/O FAST RE­
LEASE, TEST I/O, CLEAR I/O, HALT I/O, or
HALT DEVICE pertains to the device addressed by
the instruction.
The CSW has the following for,mat: CCW Address
o 4 6 8 31 : I Unit Status I Channel Status I Count
32 40 48
The fields in the CSW are allocated as follows:
Protection Key: Bits 0-3 form the protection key
used in the chain of operations at the subchannel.
63
Logout Pending (L): Bit 5, when one, indicates that
an I/O instruction cannot be executed until a pend­
ing logout condition has been cleared. Bit 45, chan­
nel control check, will always be one when bit 5 is
one.