5. The characteristic is developed from the exponent and
converted to binary.
base + = characteristic
64 + 2 =66 = 1000010 6. The fraction is converted to binary and grouped hexa­ decimally. 0.954 16 == .1001 0101 0100 7. The characteristic and the fraction are stored in the
short format. The sign position contains the sign of the
fraction. SChar Fraction
o 1000010 1001 0101 0100 0000 0000 0000 The following are sample normalized short floating-point
numbers. The last two numbers represent the smallest and
the largest positive normalized numbers.
Number Powers of 76 .E Fraction 1.0 = +1/16 x 16
1
= 0 100 0001 0001 0000 0000 0000 0000 0000 0.5 = +8/16 x 16° = 0 100 0000 1000 0000 0000 0000 0000 0000 1/64 = +4/16 x 16-
1
= 0 011 1111 0100 0000 0000 0000 0000 0000 0.0 = +0 x 16-
64 = 0 000 0000 0000 0000 0000 0000 0000 0000 -15.0 =-15/16x16
1
= 110000011111000000000000 0000 0000 5.4 x 10-
79 = 0 000 0000 000100000000 0000 0000 0000 7.2xl0
75 ';t (1-16-
6
)x16
63 0 1111111111111111111111111111111
Instruction-Use Examples
The following examples illustrate the use of many System/370
instructions. Before studying one of these examples, the
reader should first consult the instruction description in this
manual for the particular instruction of interest to him. Please note that this publication, and the instruction-use
examples, are written principally for assembly-language pro­ grammers, to be used in conjunction with the appropriate
assembly-language manuals.
For clarity, and for ease in programming, each example in
this section presents the instruction both as it is written in
an assembly-language statement and as it appears when
assembled in storage (machine format).
Machine Format
As a rule, all machine format numerical operands are written
in hexadecimal notation unless otherwise specified. Hexa­ decimal operands are shown converted into binary, decimal,
or both, if such conversion helps to clarify the example for
the reader. Storage addresses are also given in hexadecimal.
Assembly-Language Format
In assembly-language statements, registers, lengths, and
masks are all presented in decimal, but displacements may
be in hexadecimal or decimal. (A hexadecimal displacement
is indicated by X'n', where n can range from OOO-FFF.) Im­ mediate operands are normally shown in hexadecimal. When-
ever the value in a register or storage location is referred to
as "not significant," this value is replaced during the execu­ tion of the instruction.
When SS-format instructions are written in System/370
assembly language, lengths are given as the total number of
bytes in the field. This differs from the machine definition,
in which the length field specifies the number of bytes to
be added to the field address to obtain the address of the
last byte of the field. Thus, the machine length is one less
than the assembly-language length. The assembly program
automatically subtracts one from the length specified when
the instruction is assembled.
In some of the examples, symbolic addresses are used in
order to simplify the examples. In assembly-language state­ ments, a symbolic address is represented as a mnemonic
term written in all capitals, such as FLAGS, which is used
to denote the address of a storage location used to contain
data or program-control information. When symbolic ad­ dresses are used, the assembler supplies actual base and dis­ placement values according to the USING and DROP assembler instructions.
When symbolic addresses are used in the example, the
values for base and displacement are not shown in the
assembly-language format or in the machine-language format.
For assembly-language formats, the letter S in the labels
that designate instruction fields is used to indicate the com­ bination of base and displacement fields for an operand
address. (For example, S 1 represents the combination of
Bl and Dl.) In the machine-language format, the base and
displacement address components are shown as asterisks (*).
Add Halfword (AH)
The ADD HALFWORD instruction algebraically adds the
halfword contents of a storage location to the contents of a
register. The halfword storage operand is expanded to 32
bits after it is fetched and before it is used in the add oper­ ation. The expansion consists in propagating the leftmost
(sign) bit 16 positions to the left. For example, assume that
the contents of storage locations 2000-2001 are to be added
to register 5. Initially:
Register 5 contains 00 00 00 19 = 2510 Storage locations 2000-2001 contain FF FE == -2 1 0 Register 12 contains 00 00 18 00. Register 13 contains 00 00 01 50. The format of the required instruction is:
Machine Format Op Code R1 X
2
8
2 02 4A I 5 I ° I C 6
8
9 Assembler Format Op Code R
1
, 02 (X2, 82)
AH 5, X'680'(13,12)
Appendix I. Number Representation and Instruction-Use Examples 291

After the instruction is executed, register 5 contains 00 00 00 17 = 23 1 0 • AND (N, rJR, NI, NC)
When the lBoolean operator AND is applied to two bits, the
result is one when both bits are one; otherwise, the result
is zero. When two bytes are ANDed in System/370, each
pair of bits is handled separately; there is no connection
from one bit position to another. AND(NI) A frequent use of the AND instruction is to set a particular
bit to zero. For example, assume that storage location 4891
contains 0100 0011
2
, To set the rightmost bit of this byte
to zero without affectirig the other bits, the following
instruction can be used (assume that register 8 contains 00 00 48 90): Machine Format Op Code B1
°1
94 FE 8 001 Assembler Format Op Code 0, (B
1
), 12 NI 1 (8). X'FE'
When this instruction is executed, the byte in storage is
ANDed with the immediate byte:
Location 4891 0100 00112 Immediate byte 1111 11102
Result: 0100 00102 The resulting byte, with bit 7 set to zero, is stored in
location 4891. Condition code 2 is set.
Branch and link (BAL, BALR)
The BRANCH AND LINK instructions are commonly used
to branch to a subroutine with the option of later returning
to the main instruction sequence. For example, assume that
you wish to branch to a subroutine at storage address 1160. Also assume:
The contents of register 2 are not significant.
Register 5 <:ontains 00 00 11 50. Address 00 00 C6 contains a aAL instruction. (pSW bits 40-63
will contain 00 00 CA after of BAL)
The format of the BAL iristruction is:
Machine Format Op Code R1 X
2
B2 Assembler Format Op Code R
1
, 02 (X
2
, B
2
)
BAL 2,X'10'(O,5) 292 System/370 Principles of Operation
After the instruction is executed:
Register 2 (bits 8-31) contains 00 00 CA PSW bits 40-63 contain 00 11 60 The programmer can return to the main instruction se­ quence at any time with a BRANCH ON CONDITION (BCR)
instruction that specifies register 2 and a mask of 15
1 0 , pro­ vided that register 2 has not meanwhile been disturbed.
The BALR instruction with the R2 field equal to zero may
be used to load a register for use as a base register. For
example, in the assembly language the sequence of statements:
BALR 15,0 USING *,15
tells the assembly program that register 15 is to be used as
the base register in assembling this program and that when
the program is executed, the address of the next sequential
instruction following the BALR will be placed in the regis­ ter. (The USING statement is an assembler instruction and
is thus not a part of the object program.)
At any time, the condition code may be preserved for
future inspection with BALR 1,0. Bits 2 and 3 of the regis­ ter (Rl) contain the condition code.
Branch on Condition (BC, BCR)
The BRANCH ON CONDITION instructions test the condi­ tion code to see whether a branch should or should not be
taken. The branch is taken only if the condition code is as
specified by a mask.
Mask Condition
Value Code 8 0 4 1
2 2
1 3
For example, assume that an ADD (A, AR) operation has
been performed and you wish to branch to address 6050 if
the sum is zero or less (condition code = 0 or 1). Also
assume:
Register 10 contains 00 00 50 00 Register 11 contains 00 00 10 00 The RX form of the instruction performs the required
test (and branch, if necessary) when written as:
Machine Format Op Code M1 X
2
B2 02 I L- _4_7 -..1.-1 Assembler Format Op Code M
1
, 02 (X
2
, B
2
)
BC 12,X'50'( 11,1 0) A mask of 15 indicates a branch on any condition (an
unconditional branCh). A mask of zero indicates that no
branch is to occur (a no-operation).