Register 6 does not contain all zeros
The initial contents of register 7 are not significant
Register 8 contains 00 00 35 50 The following assembly language statements load the reg­ isters properly and perform the divide operation:
Statement Comments
L 6,0(0,8) Places 00 00 08 07 into register 6 SROA 6,32(0) Shifts 00 00 08 07 into register 7
Register 6 is filled with zeros (sign bits)
° 6,4(0,8) Performs the division
The machine format of the preceding DIVIDE instruction
is:
Machine Format 004 After the foregoing instructions are executed:
Register 6 contains 00 00 00 14 = 20 1 0 = the remainder
Register 7 contains 00 00 00 2D = 4510 == the quotient
Note that if the dividend had not been first placed in regis­ ter 6 and shifted into register 7, register 6 would not have
been filled with the proper sign bits (zeros in this example),
and the DIVIDE instruction would not have given the
expected results. Exclusive OR (X, XR, XI, XC)
When the Boolean operation EXCLUSIVE OR is applied to
two bits, the result is one when one, and only one, of the
two bits is one; otherwise, the result is zero. When two
bytes are EXCLUSIVE ORed in System/370, each pair of
bits is handled separately; there is no connection from one
bit position to another.
Exclusive OR (XI) A frequent use of the EXCLUSIVE OR (XI) instruction is
to invert a bit (change a zero bit to a one or a one bit to a
zero). For example, assume that storage location 8082 contains 0110 1001
2
, To set the leftmost bit to one and
the rightmost bit to zero without affecting any of the other
bits, the following instruction can be used (assume that
register 9 contains 00 00 80 80): Machine Format Op Code 12 B1
97 81 9 002 Assembler Format Op Code 01 (81)' 12 XI 2(9),X'81'
When the instruction is executed, the byte in storage is EXCLUSIVE ORed with the immediate byte:
Location 8082: 0110 1001 2 Immediate byte: 1000 00012 Result: 1110 10002 The resulting byte with the leftmost and rightmost bits
inverted is stored in location 8082. Condition code 1 is
set.
Exclusive OR (XC)
The EXCLUSIVE OR (XC) instruction can be used to
change the contents of two areas in storage without the use
of an intermediate storage area. For example, assume that
two words are in storage:
Word 1 Word 2
358 35B 360 363 I 00 I 00 1
17
1
90 I 1 00 1 00 1141 01 I Execution of the instruction (assume that register 7 con­ tains 00 00 03 58):
Machine Format Op Code L
07 03 000 008 Assembler Format Op Code 01 (L, B
1
), 02 (B
2
)
XC 0(4,7) ,8(7) EXCLUSIVE ORs word 1 with word 2 as follows:
Word 1: 0000 0000 0000 0000 0001 0111 1001 00002 = 00 00 17 90 Word 2: 0000 0000 0000 0000 0001 0100 0000 00012 = 00 00 14 01 ResuU: 0000 0000 0000 0000 0000 0011 1001 00012 = 00 00 03 91
The result replaces the former contents of word 1.
Now, execution of the instruction
Machine Format Op Code L B1
°1
B2 °2
07 03 I 7 008 I 7 I 000 Assembler Format Op Code 01 (L,B
1
),02(B
2
)
XC 8(4,7) ,0(7) produces the following result:
Word 1: 0000 0000 0000 0000 0000 0011 1001 00012 = 00 00 03 91
Word 2: 0000 0000 0000 0000 0001 0100 0000 0001 2 = 00 00 14 01 Result: 0000 0000 0000 0000 0001 0111 1001 00002 = 00 00 17 90 Appendix I. Number Representation and Instruction-Use Examples 297

The result of this operation replaces the former contents of
word 2. Word 2 now contains the original value of word 1.
Lastly, execution of the instruction
Machine Format Op Code L Bl Dl B2 02 Assembler Format OpCode 01 (L,B
1
),02(B
2
) XC 0(4,7),8(7)
produces the following result:
Word 1: 0000 0000 0000 0000 0000 0011 1001 00012 :=00 00 03 91
Word 2: 0000 0000 0000 0000 0001 0111 1001 00002 := 00 00 17 90 Result: 0000 0000 0000 0000 0001 0100 0000 00012 := 00 00 14 01 The result of this operation replaces the former contents of
word 1. Word 1 now contains the original value of word 2.
Notes:
1. With the XC instruction, fields up to 256 bytes in length
can be exchanged.
2. With the XR the contents of two registers
can be exchanged.
3. Because the X instruction operates storage-to-register
only, an exchange cannot be made solely by the use of
x.
4. A field EXCLUSIVE ORed with itself is cleared to zeros.
Execute (EX)
The EXECUTE instruction causes one instruction in main
storage to be executed out of sequence without actually
branching to the object instruction. EXECUTE may be
used to supply the length field for an SS instruction without
modifying the SS instruction in storage. For example, as­ sume that a MOVE (MVC) instruction is located at address 3820, with a fonnat as follows:
Machine Format Op Code L Bl Dl B2 02 Assembler Format OpCode Dl (L,B
1
),D2(B
2
) MVC 3(1,12),0(13)
where register 12 contains 00 00 89 13 and register 13
contains 00 00 90 AO. Further assume that at storage address 5000, the following EXECUTE instruction is located:
298 System/370 Principles of Operation
Machine Format
44 11 1 0 I A 000 A sse mbler Format Op Code R
1
, D2 (X
2
, B
2
)
EX 1,0(0,10) where register 10 contains 00 00 38 20 and register 1 con­ tains 00 OF FO 03. When the instruction at 5000 is executed, bits 24-31 of
register 1 are ORed with bits 8-15 of the instruction at 3820: Bits 8-15: 0000 00002 = 00 Bits 24-31: 0000 00112 = 03 Result: 0000 0011
2 = 03 causing the instruction at 3820 to be executed as if it orig­ inally were:
Machine Format Op Code L
D2 03 I C I Assembler Format Op Code Dl (L, B
1
), D2 (B
2
) MVC 3(4,12),0(13)
However, after execution:
Register 1 is unchanged 003 [he instruction at 3820 is l.lflchanged D 000 The contents of the four bytes starting atlocation 90AOhave been
moved to the four bytes starting at location 8916
The CPU next executes the instruction at address 5004 (PSW bits 40-63 contain 00 50 04) Load (L, LR)
The LOAD instructions place, unchanged, the contents of
a word in storage or of a register into another register. For
example, assume that the four bytes starting with location 21004 (a fullword boundary) are to be loaded into register 10. Initially:
Register 5 contains 00 02 00 00 Register 6 contains 00 00 10 04 The contents of register 10 are not significant
Storage locations 21004-21007 contain 00 00 AB CD
To load register 10, the RX form of the instruction can
be used:
Machine Format Op Code Rl X
2
B2 000 Assembler Format Op Code R
1
, D2 (X
2
, B
2
)
L 10,0(5,6)