characters from the EBCDIC code. For example, in EBCDIC the above two data fields are:
Field 1 JOHNSON ,A.B.
Field 2 JOHNSON,A.C. Condition code 1 tells us that A. B. JOHNSON precedes
A. C. JOHNSON, thus placing the names in the correct
alphabetic order.
Compare logical Characters Under Mask (ClM)
The CLM instruction provides a means of comparing selected
bytes of a word contained in a general register to a contig­
uous field of bytes in main storage. The M3 field of the CLM instruction is a four-bit mask that selects zero through four
bytes from a general register, each mask bit corresponding
left to right with a selected register byte. In the compari­
son, the selected register bytes are treated as a contiguous
field, and the operands are considered as binary unsigned
quantities, with all codes valid. The operation proceeds
left to right. For example, assume that:
Three bytes starting at storage location 10200 contain FO BC 7B
Register 12 contains 10 000 Register 6 contains FO BC 5C 7B
Execution of the instruction
Machine Format 200 Assembler Format Op Code R
1
, M
3
, D2 (8
2
) ClM 6,8'1101',X'200'(12) produces the following result:
Register 6: FO Mask (D) FO Three bytes starting at location 10200 8C 8C 5C o
78
1
78
Result: Condition code 0 is set (selected bytes are equal,
or mask is zero). Register 6 and bytes in main
storage are unchanged. Other condition codes would indicate:
Condition Code,'
1 Selected field of first operand (register contents)
is less than second operand (storage locations)
2 Selected field of first operand is greater than
second operand
3
Compare logical long (ClCL)
The CLCL instruction is used to logically compare two
operands in main storage. Each operand can be up to
16,777,215 bytes in length. Two pairs of even-odd general
registers are used to locate the operands and to control the
execution of the CLCL instruction, which can be inter­
rupted in progress. The first register of each pair must be
an even register, and it is used to contain the storage location
of the byte currently being compared in each operand. The
odd register of each pair contains the length of the operand
it covers, and the high-order byte of the second-operand
odd register contains a padding character which is used to
logically extend a shorter operand to the same length as a
longer operand. The following illustrates the assignment of
registers for CLCL: R1 (Even) First-Operand Address I 0 8 31
R1+1 (Odd) First-Operand length I 0 8 31
R2 (Even) Second-Operand Address 0 8 31
R2+1 (Odd) Pad Char. Second-Operand length
o 8 31
The following instructions set up two register pairs to
control a text-string comparison. For example, assume: Operand 1
Address: 20800 (hex)
Length: 100 (dec) Operand 2
Address: 20AOO (hex)
Length: 132 (dec) Pad Character
AddIess: 20003 (hex)
Length: 1
Value: 40 (hex)
Register 12 contains 00 02 00 00 The setup instructions are:
LA 4,X'800' (12) Point register 4 to the start of the first
operand
LA 5,100 Set register 5 to the length of first operand
LA 8,X'AOO'(12) Point register 8 to the start of second
operand
LA 9,132 Set register 9 to the length of second
operand
ICM 9,B'1000',3(12) Insert padding character (blank) into byte
o of register 9.
The register pair 4-5 is now covering the first operand.
Bits 8-31 of register 4 contain the storage location of the
start of an EBCDIC text string, and bits 8-31 of register 5
contain the length of the string, in this case 100 bytes.
Appendix I. Number Representation and Instruction-Use Examples 295

The register pair 8-9 covers the second operand with bits
8-31 of register 8 containing the length of the second oper­
and, in this case 132 bytes. Bits 0-7 of register 9 contain
an EBCDIC blank character (X'40') to logically pad the
shorter operand. In this example, the blank padding char­
acter is used in the first operand, after the 100th character,
to compare with the remaining characters in the second
operand.
With the 4-5 and 8-9 register pairs thus set up, the format
of the CLCL instruction is:
Machine Format Op Code R1 R2 OF Assembler Format Op Code 1=l1' R2
CLCL 4,8 When thiis instruction is executed, the comparison starts
at the high-order end of both operands and proceeds to the
right. The operation ends as soon as an inequality is de­
tected or the end of the longest operand is reached.
If this ClLCL instruction is interrupted after 60 bytes are
successfully compared, the operand lengths in registers 5
and 9 are decremented to X'28' and X'48', respectively,
and the operand locations in registers 4 and 8 are incre­
mented to X'2083C' and X'20A3C'. When the CLCL instruction is reexecuted, the comparison begins at the
point of interruption.
If the instruction is interrupted after 110 bytes are suc­
cessfully compared, the operand lengths in registers 5 and
9 are decremented to 0 and X'16', respectively, and the
operand locations in registers 4 and 8 are incremented to
X'2086E' and X'20A6E'. . When the comparison ends, the condition code indicates
the result. The condition code settings are as follows:
Condition Code:
o Operands are equal, or both field lengths are
zero
2
3
First operand is low
First operand is high
When the operands are unequal, the address fields of regis­
ters 4 and 8 can be used to locate the bytes that caused the
mismatch. The byte count fields in registers 5 and 9 can be
used to determine how far the comparison progressed suc­
cessfully.
Convert to Binary (CVB)
The CONVERT TO BINARY instruction converts an eight­
byte, signed, packed-decimal number into a siglied binary
number and loads the result into a general register. After
296 System/370 Principles of Operation
the conversion operation is completed, the number is in the
proper form for use as an operand in fixed-point arithmetic.
For example, assume:
Storage locations 7608-760F contain a positive packed-decimal
number, 00 00 00 00 00 25 59 4C
The contents of register 7 are not significant
Register 13 contains 00 00 76 00 The format of the conversion instruction is:
Machine Format Op Code R1 X
2
8
2 008 Assembler Format Op Code R
1
, 02 (X
2
, 82)
CV8 7,8(0,13) After the instruction is executed, register 7 contains 00 00 63 FA = + 25,594 10 . Convert to Decimal (CVD)
The CONVERT TO DECIMAL instruction performs func­
tions exactly opposite to those of the CONVERT TO BINARY instruction. CVD converts a binary number in a
register to packed decimal and stores the result in a double­
word. For example, assume:
Register 1 contains 00 00 OF OF = 385510 Register 13 contains 00 00 76 00 PSW bit 12 = 0 (EBCDIC mode)
The format of the instruction is:
Machine Format Op Code R1 X
2
8
2 02 4E 11 1 0 I ° 008 Assembler Format Op Code R
1
, 02 (X
2
, 82) CVO 1,8(0,13) After the instruction is executed, locations 7608-760F contain 00 00 00 00 00 03 85 5C. The plus sign generated is the standard EBCDIC plus sign, 1100
2
• Divide (0, DR)
The DIVIDE instruction divides a dividend in an even/odd
register pair by the divisor in a register or in storage. Since the dividend is assumed to be 64 bits long, it is important
that the proper sign be first affixed. For example, assume
that:
Storage locations 3550-3553 contain 00 00 08 D7 = 227010 = the
dividend
Storage locations 3554-3557 contain 00 00 00 32 = 5010 = the
divisor