Case 3: Register 3 contains FF FF FF FD
If the scale factor is -3, FIELD4 represents
127 x 10..,3 = 0.127 FIELD4 (after): 00 00 00 01 3C
The implied decimal point is now shifted two places
to the left; because the shift was to the righi.
FIELD4 is rounded to the nearest two deciinal
places.
In the preceding cases, the implied decimal is shifted two
places to the left, under control of the D2 field in the SRP instruction. The shifting is controlled by the address that is
resolved when the contents of the base register (GR 3) are
added to the displacement D2, effecting the multiplication
of FIELD4 by a variable power of 10. Zero and Add (ZAP)
Assume that the signed, packed-decimal field at storage lo­ cations 45004502 is to be moved to locations 4000-4004 with four leading zeros in the result field. Also assume:
Register 9 contains 00 00 40 00 Storage locations 4000-4004 contaIn 12 34 56 78 90 Storage locations 4500-4502 contain 38 46 OD After the instruction
Machine Format
F8 I 4 I 2 I 9 000 500 Assembler Format Op Code 01 (L1, 8,)' 02 (L2' 82) ZAP 0(5,9),X'500'(3,9) is executed, the storage locations 4000-4004 contain 0000 3846 OD; condition code 1 is set to indicate a negative re­ sult. Note that because the first operand is not checked for
valid sign and digit codes, it may contain any combination
of hexadecimal digits. FLOATING-POINT INSTRUCTIONS In this section, the abbreviations FPRO, FPR2, FPR4, and FPR6 stand for floating-point registers 0, 2,4, and 6,
respectively.
Add Normalized (AE, AER, AD, ADR)
The ADD NORMALIZED instructio.ns perform the addition
of two floating-point numbers and place the normalized re­ sult in a floating-point register. Neither of the two numbers
to be added must necessarily be normalized before addition
occurs. For example, assume that:
FPR6 contains 43 08 21 00 00 00 00 00 = 82.1
16 == approximately 130.06
10 Storage locations 2000-2007 contain 41 12 34 56 00 00 00 00 = 1.23456
16 == approximately 1.13
10 (normalized)
Register 13 contains 00 00 20 00 The instruction
Machine Format 000 Assembler Format Op Code R
1
, 02 (X
2
, 82)
AE 6,0(0,13) can be used to perform the short-precision addition of the
two operands. In this example, the instruction operates as
follows:
The characteristics of the two numbers are compared. Since the number in storage has a characteristic that is smaller
by 2, it is right-shifted after fetching until the characters
agree. The two numbers are then added:
FPR6: 43 08 21 00 Guard
Digit Shifted number from storage: 43 00 12 34 5
Intermediate sum: 43 08 33 34 5
Because the intermediate sum is unnorinaiized, it is left­ shifted to form the normalized floating-point number 42 83
33 45 (= 83.3345
16 = 131.2
10
), This number replaces the
high-order portion of FPR6. The low-order portion of FPR6 and the contents of storage locations 2000-2007 are
unchanged.
If the long-precision instruction AD is used, the result in FPR6 will be 42 83 33 45 600000 dO. Note that, in this
case, the use of the long-precision instruction provides one
additional hexadecimal digit of precision.
Add Unnormalized (AU, AUR, AW, AWR) The ADD UNNORMALIZED instructions operate identi­ cally to the ADD NORMALIZED instructions, except that
the final result is not normaHzed when ADD UNNORMAL­ IZED is used. For example, using the same operands as in
the example for ADD NORMALIZED, when the short­ precision instruction
Machine Format
7E I 6 I 0 I ° I 000 Appendix I. Number Representation and Instruction-Use Examples 309

Assembler Format Op Code R
l
, D2 (X
2
, 8
2
)
AU 6,0(0,13)
is executed, the two numbers are added as follows: FPR6: 43 08 21 00 Guard
Digit
Shifted number from storage: 43 00 12 34 5
Sum: 43 08 33 34 5
The guard digit participates in the addition but is dis­ carded. The unnormalized sum replaces the high-order por­ tion of FPR6.
If the result in FPR6 is converted to a normalized number
(42 83 33 40 00 00 00 00) and is compared to the result in
FPR6 when ADD NORMALIZED was used (4283 3345 00 0000(0), it is apparent in this case that the use of ADD
NORMALIZED (with the retention of the guard digit) has
preserved some additional significance in the result. COmparE! (CE, CER, CD, CDR)
Assume that FPR4 contains 43 00000000000000 ( = 0), and FPR6 contains 34 12 34 56 78 9A BC DE (a positive
number). The contents of the two registers are to be com­ pared with the following long-precision instruction:
Machine Format Op Code Rl R2 Assembler Format Op Code R
l
, R2 CDR 4,6
When this instruction is executed, the number with the
smaller characteristic is taken from the register and right­ shifted until the two characteristics agree. The shifted con­ tents of FPR6 are 43 00000000000000, with a guard
digit of zero. Therefore, when the two numbers are com­ pared, condition code 0 is set, indicating an equality.
As the above example implies, when floating-point num­ bers are compared, more than two numbers may compare
equally if one of the numbers is unnormalized. For example,
the unnormalized floating-point number 41 00 1234 56 78
9A BC compares equally with all numbers of the form 3F
12 34 56 78 9A BC OX (X represents any hexadecimal num­ ber). When the COMPARE instruction is executed, the two
low-order digits are shifted right two places, the 0 becomes
the guard digit, and the X does not participate in the
comparison.
Note, however, that when two normalized floating-point
numbers are compared, the relationship between numbers
that compare equally is unique: each digit in one number
must be identical to the corresponding digit in the other
number. 310 System/370 Principles of Opera tion MULTIPROCESSING EXAMPLES
Compare and Swap (CS, CDS) The COMPARE AND SWAP and COMPARE DOUBLE AND
SWAP instructions can be used in multiprogramming or
multiprocessing environments to serialize access to counters,
control words, and other common storage areas.
Setting a Single Bit
In a multiprocessing system, two central processors have
access to the same main storage, and both can fetch, modify,
and store data in the same locations (such as in a system con­ trol block). In this configuration, if the OR (immediate) in­ struction is used to modify storage, such as when setting a
flag bit, program logic errors may occur.
Example of a Program Failure Using OR Immediate
Assume that two independently processing programs wish to
set different bits to one in a common byte in storage. The
following example shows how the use of the instruction OR immediate (01) can fail to accomplish this, if the programs
are executed nearly simultaneously on two different CPUs. One of the possible error situations is depicted.
Execution of Instruction 01 FLAGS,X'01' on CPU A
Fetch FLAGS X'OO' OR X'Ol' into X'OO' Store X'Ol' into FLAGS Execution of Instruction 01 FLAGS,X'80' on FLAGS CPU B X'OO' X'OO' X'OO' X'OO' X'80' X'Ol' Fetch FLAGS X'OO' OR X'80' into X'OO' Store X'80' into FLAGS FLAGS should have value of X'8l' following both updates.
The problem shown here is that the value stored by the 01 instruction executed on CPU A overlays the value that was
stored by CPU B. The X'80' flag bit was erroneously turned
off, and the program executing on CPU B now has invalid
data.
The COMPARE AND SWAP (CS) instruction is included
in System/370 to overcome this and similar problems. The CS instruction first checks the value of a storage location
and then modifies it only if it is the same as the program
expects; normally, this would be a previously fetched value.
If the location is not what the program expects, then the lo­ cation is not modified, but rather the current value of the
location is loaded into a general register, in preparation for
the program to loop back and try again. During the CS execution, no other CPU can access the subject storage
location.
The following instruction sequence shows how the CS in­ struction can be used to update a single bit in storage.
Assume that FLAGS is the first byte of a word in storage
called "WORD."