LA 6,X'80' Put bit to be ORed into register 6 SLL 6,24 Shift left 24 places to align the byte
to be ORed with the location of FLAGS within WORD L S,WORD Get original flag bit values
RETRY LR 4,5 Put flags to modify into register 4 OR 4,6 Turn on bit in new copy of flags CS S,4,WORD Store new flags unless original flags
were changed
BNE RETRY If new flags not stored, try again
The format of the CS instruction is:
Machine Format Op Code S1 BA ****
Assembler Format Op Code R
1
, R
3
, S1 CS 5,4,WORD
The CS instruction compares the first operand (register 5
containing the original flag values) to the second operand
(word) while storage access to the subject location is not
permitted to any CPU other than the one executing the CS instruction.
If the compare is successful, indicating that FLAGS still
has the same value that it originally had, the modified copy
in register 4 is stored into FLAGS. If FLAGS has changed
since it was loaded, the compare will not be successful, and
the current value of FLAGS is loaded into register S.
The CS instruction sets condition code 0 to indicate a
successful compare and swap, and condition code 1 to indi­ cate an unsuccessful compare and swap.
The program executing the example instructions tests the
condition code following the CS instruction and reexecutes
the flag-modifying instructions if the CS instruction indi­ cated an unsuccessful comparison. When the CS instruction
is successful, the program continues execution outside the
loop and FLAGS contains valid data.
Updating Counters
In this example, a 32-bit counter is updated by a program
using the CS instruction to ensure that the counter will be
correctly updated. The original value of the counter is ob­ tained by loading the word containing the counter into a
register. The original counter is then moved into another
register to provide a modifiable copy, and a register (con­ taining an increment to the counter) is added to the modi­ fiable copy to provide the updated tounter value. The CS instruction is then used to ensure a (-'".lid store of the
counter. The following instruction sequence performs this
procedure:
LA
L LOOP LR
AR
6,1
S,CNTR
4,5
4,6
Put increment (1) in register
Get original counter value Set up copy to modify Update counter in register CS 5,4,CNTR
BNE LOOP Page of GA22-7000-4 Revised September 1,1975
By TNL: GN22-0498 Update counter in storage
If original value changed, update new
value
CNTR (before): 00 00 00 10
CNTR (after): 00 00 00 11
The program updating the counter byte then checks the
result by examining the condition code. Condition code 0 indicates a successful update, and the program can proceed.
If the counter byte had been changed between the time that
the program loaded its original value and the time that it
executed the CS instruction, the CS instruction would have
loaded the new control byte value into register 5 and set
the condition code to 1, indicating an unsuccessful update.
The program would then have to update the new counter
value in register 5 and retry the CS instruction, retesting the
condition code, and retrying, until a successful update is
completed.
The following shows two CPUs, A and B, executing the
above program simultaneously. That is, both CPUs desire
to add one to CNTR. CPUA Reg4 Reg5
16 16
16 16
17 16
17 16 CPUB Comments
CNTR Reg4 Reg5
16
16
16
16
16
17
17
18
16
17
17
18
18
16
16 CPU A loads RegS and Reg4
from CNTR CPU B loads Reg5 and Reg4
from CNTR CPU B adds 1 to Reg4 CPU A adds 1 to Reg4 CPU A executes CS; successful
match store
17 CPU B executes CS; no match,
Reg5 changed
17 CPU B loads RegS into Reg4
and adds 1 to Reg4
17 CPU B executes CS; successful
match store
EXAMPLES OF THE USE OF COMPARE AND SWAP The following examples of the use of the COMPARE AND
SWAP instruction illustrate the applications for which the
instruction is intended. It is important to note that these
are examples of functions that can be performed by pro­ grams running enabled or by programs that are running on
a shared-main-storage multiprocessor. I Interlocked Sing1e-Word, or Smaller, Serially Reusable Resource (SR R)
The following routine allows a program to modify the con­ tents of a storage location while running enabled, even
though the possibility exists that another CPU may simul­ taneously update the same location and even though the
routine may be interrupted by another program that updates
the location.
Appendix I. Number Representation and Instruction-Use Examples 311

Page ofGA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 SRR UPDATE Routine
Initial conditions:
General register (GR) 2 contains the address of the word
to be updated. L 3,0(2) FETCH THE WORD TRY AGN LR 4,3 MOVE IT TO GR4
[ANY INSTRUCTION] MODIFY GR4 (e.g., add a constant,
set a bit, etc.) CS BNE
3,4,0(2) STORE THE NEW VALUE IF THE WORD HAS NOT CHANGED
TRYAGN
The branch to TRY AGN is different from "bit-spinning" in that the branch will be taken only if some other program modifies the update location. If a number of CPUs simul­
taneously attempt to modify one location, one CPU will
fall through the loop, another will loop once, and so on until
all CPUs have succeeded.
Bypassing POST The following routine allows the SVC "POST" as used in OS/VS to be bypassed whenever the corresponding WAIT
has not yet been issued, provided that the supervisor WAIT
and POST routines use COMPARE AND SWAP to manipu­
late event control blocks (ECBs). BYPASS POST Routine
Initial conditions:
GRl contains the address of the ECB. GRO contains the POST code. HSPOST L 3,0(1) GR3 = CONTENTS OF ECB
LTR 3,3 ECB MARKED 'WAITING'
BM PSVC YES, ISSUE AN SVC CS 3,0,0(1) NO, STORE POST CODE BE EXIT CONTINUE PSVC SVC POST ECB ADDRESS IS IN GRl, POST CODE IN GRO EXIT [ANY INSTRUCTION] A corresponding bypass WAIT function, using TM, is in
use at present.
The following routine may be used in place of the previous HSPOST routine if the ECB is assumed to contain zeros
when it is not "WAITING." HSPOST SR 0,0 CS 0,2,0(1) BE EXIT SVC POST EXIT [ANY INSTRUCTION] Lock/Unlock When SRRs larger than a doubleword are to be updated, it
is usually necessary to provide special interlocks to ensure
312 System/370 Principles of Operation
that a single program at a time updates the SRR. In general,
updating a list, or even scanning a list, cannot be safely
accomplished without first "freezing" the list. However,
the COMPARE AND SWAP instructions can be used in
certain restricted situations to perform queuing and list
manipulation. Of prime importance is the capability to per­
form the lock/unlock functions and to provide sufficient
queuing to resolve contentions, either in a LIFO or FIFO manner. The lock/unlock functions can then be used as the
interlock mechanism for updating an SRR of any complexity.
The lock/unlock functions are based on the use of a header
associated with the SRR. The header is the common starting
point for determining the states of the SRR, either free or
in use, and is also used for queuing requests when con­
tentions occur. Contentions are resolved using WAIT and POST. Although the examples do not show it, it is expected
that the BYPASS WAIT and BYPASS POST would be used.
The general programming technique requires that the pro­
gram that encounters a locked SRR must "leave a mark on
the wall" indicating the address of an ECB on which it will
WAIT. The program "unlocking" sees the mark and posts
the ECB, thus permitting the waiting program to continue.
In the two examples given, all programs using a particular SRR must use either the LIFO queuing scheme or the FIFO scheme; the two cannot be mixed. When more complex
queuing is required, it is suggested that the queue for the SRR be locked using one of the two methods shown. Lock/Unlock with LIFO Queuing for Contentions
The header consists of a word, which can contain zero, a
positive value, or a negative value. • A zero value indicates that the SRR is free. • A negative value indicates that the SRR is in use but no
additional programs are waiting for the SRR. • A positive value indicates that the SRR is in use and that
one or more additional programs are waiting for the SRR.
Each waiting program is identified by an element in a
chained list. The positive value in the header is the address
of the element most recently added to the list. . Each element consists of two words. The first word is used
as an ECB; the second word is used as a pointer to the next
element in the list. A negative value in a pointer indicates
that the element is the last element in the list. The element
is required only if the program finds the SRR locked and
desires to be placed in the list.
The following char
f . scribes the action taken for LIFO LOCK and LIFO UNLOCK routines.