external interruption (continued)
mask (BC mode) 34
mask (EC mode) 34
time-of-day clock sync check 88
external signal, interruption 87
mask bit (in control register 0) 87
failing-storage address
in machine-check extended interruption information 177
in machine-check interruption code validity bits 180 features, System/370 (see Appendix A)
fetch protection bit (see also storage protection) 38
fetch reference, storage operand 25
field (see instruction format)
field validity flags (in limited channel logout) 241
fill character 151
fixed-length operands 14
fixed logout (see machine-check fixed logout)
fixed-point
divide exception 78
exceptions 78
number representation 116
overflow exception 78
flag in CCW
as defined for each type of command 217
chain command 211
chain data 211
program-controlled interruption (PCI) 211
skip 211
suppress-length indication (SLI) 211
floa ting-poin t
divide exception 161, 79
instructions 157, 290 data format 157
examples 309 exceptions 159, 79
number representation 159
register 16
register valid bit (in machine-check interruption code) 180 register save area (machine-check extended interruption
information) 178
format
data 14
dynamic address translation 68
information 14
instruction 20 1/ 0 instruction 197
summary (see Appendix D)
word 14
formation of the real address 62
forming the operand address 21
fraction in floating-point operands 157
functions that differ from System/360 (see Appendix B)
general instructions 116
data formats 116
representation of fixed-point numbers 116
general-purpose design of System/370 9
general register 16
coupled 16
save area (machine-check extended interruption
information) 178
valid bit (machine-check interruption code) 180 general-register-alteration program event 43
guard digit, floating-point 158 Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
halfword (definition) 14
HALT DEVICE (HDV) instruction 199
HALT I/O (HIO) instruction 202 HALVE (HDR, HER) instruction 164
handling of access exceptions, 81
handling of (storage) addresses 63
hardware checkpoint (in CPU retry) 172
hardware instruction retry (see CPU retry)
hexadecimal tables (see Appendix G)
I field in an instruction 19
IDAW (indirect data address word) 216
identification of source of interruption 70 identity of storage control unit (SCU), in limited channel
logout 240 immediate operand 20,19 immediate operation (I/O) 222 IMPL (initial microprogram load) controls 245
implicit (address) translation 60 implied field length of operands 14
inadvertent resetting of sense data (see unit check programming
note) 233
incorrect length, channel status condition 233
index (in operand designation) 20 indirect data address (IDA) 190,216
flag (in CCW) 211
word (lDAW) 216
information
formats 14
positioning 15
initial-CPU-reset order 98
initial-micro program-load (lMPL) controls 245
order 98
initial program load (lPL) 54
initial-program-reset order 97
input/ output
address, in limited channel logout 242
commands 217
communications area (IOCA) 239
device 186
addressing 192
attachment of 186
error 197
devices and control units 186
error alert, in limited channel logout 241
extended logout control bit (in control register 14) 182
extended logout pointer 240 general description 17
instructions 197
interface 17
interruption 226, 73
channel available (CAl) 227
channel mask 88
conditions 226
priority of 227
program-controlled (PCI) 233
mask
Be mode (see extended control mode) 33
EC mode 34
operations 185
blocking of data 210 chaining 213
conclusion (termination) due to equipment
malfunction 226
Index 319

Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 input/output (continued)
operations (continued)
conclusion of 222
initiation 210 termination by HALT I/O, HALT DEVICE 224
selective reset 195 system operation 189 reset 194, 51
input/output status condition 229, 239
input/output system states 192 INSERT CHARACTER (lC) instruction 130 INSERT CHARACTERS UNDER MASK (ICM) instruction 130 INSERT PSW KEY (IPK) instruction 104 INSERT STORAGE KEY (lSK) instruction 105 instruction
address in PSW BC mode 34
EC mode 35
validity bit 180 address, updated 22
address validity bit (machine-check interruption code) 180 B fidd 20 counter (instruction address portion of current PSW) 35
D field 20 decimal 147
exception handling, I/O 210 execution 22, 74
conceptual sequence (order) of 22
fetching 23
fetching program event 42 field, zero value in X or B 22
fixed-point (see general instructions)
floating-point 157
format 20 basic 20 I/O 197
general US I field 19
input/output 197
length code (ILC) in PSW in BC mode PSW 34
meaning 71 logical (see general instructions)
ope:rand 19
ope:ration 20 privileged 30 R field 19
sets and features 9
system controi i03 use examples 291
X field 20 instruction processing damage (machine-check interruption
condition) 178,175
instructions (see Appendix C for listings)
instructions
interruptible 73
offered by some models, but not listed in this manual 76
integral! boundaries in main storage 15
interface
address validity flag 241
control check, channel status condition 235 I/O 17 interlocked update storage reference 26
interlocks between logical and real storage references 63 interlocks between storage references 64
interpretation of order code, conditions precluding 98 320 :System/370 Principles of Operation
interrupt key 245, 86
interruption 86
mask bit (in control register 0) 86
priority of interruption 86
interruptible instructions 75
interruption (to program execution) 70 classes 70 clock comparator 47
code, BC mode PSW 34 CPU timer 48
enabling and disabling 70 external 84
general description 22
instruction length code use 71 I/O (input/output) 88
machine-check 75
new PSW 90,23 old PSW 90, 23
point of (machine check) 176
point of (occurrence of) 74
priorities 89
program 75
program-controlled 215
purpose 70 restart 88
source identification 70 supervisor-call 84
interruption action 70 machine check 175
table 72
interruption classes
external 84
input/output 88
machine check 75
program 75
supervisor-call 84
interruption, machine check 175
conditions 175
extended information 177
interruption code 178
interruption pending (I/O system state) 192
in channel 194
in device 193
in subchannel 194
interruptions, multiple PCI (see programming notes) 221
interval timer 49
external interruption 49,86
mask bit (in control register 0) 86
priority of interruption 86
updating 49
intervention required (sense data) 220 invalid address 76
invalid CBC
definition 172
handling of
in keys in storage 173
in registers 173
in storage 172
invalid (I/O programming) 234
invalid order status bit 100 I/O (see input/output) I/O interface 17 IOCA (input/output communications area) 240 10EL (input/output extended logout)
address in main storage 91