The new PSW as introduced by an interruption or
instruction becomes active (that is, the information
introduced into the currentPSW assumes control
over the system) at the completion of the interrup
tion or at the completion of the execution of the
instructiori, respectively. The interruption forprogram"-event recording associated with an irlstruc
tion that changes thePSW occurs under control of
thePSW mask that is effective at the beginning of
the operation.
The figures below showPSW formats in the BC
and EC modes.
Program Status Word Format in Be
Mode
The BC mode is specified by a zero inPSW bit posi
tion 12. The following is a summary of the functionsof the PSW fields.
Channel Masks 0-5: Bits0-5 control whether the CPU is enabled for I/O interruptions from channels 0-5, respectively. When the bit is zero, the channel
cannot cause an110 interruption. When the bit is
one, a condition at the channel can cause anI/O . interruption.
oChannel Masks 0-5 16
Input/Output Mask(10): Bit 6 controls whether
theCPU is enabled for I/O interruptions from chan
nels 6 and higher. When the bit is zero, these chan
nels cannot causeI/O interruptions. When the bit is
one,I/O interruptidns are subject to the channel-
mask bits of the corresponding channels in control
register 2: when the channel-mask bit is zero, the
channel cannot causeI/O interruption; when the
channel-mask bit is one, a condition at the channel
can cause an interruptiori.
External Mask (E): Bit 7 controls whether theCPU is enabled for interruption by conditions included in
the external class. When the bit is zero, an external
interruption cannot occur. When the bit is one, an
external interruption is subject to the corresponding
external subclass-mask bits in control register0: when the subclass-mask bit is zero, conditions asso
ciated with the subclass cannot cause an interrup
tion; when the subclass-mask bit is one, an interrup
tion in that subclass can occur.
Protection Key: Bits 8-11 form theCPU protection
key. The key is matched with a key in storage when
ever information is stored, or whenever information
is fetched from a location that is protected against
fetching.Interruption Code
31I nstruction Address
32 34 3640 63 PSW Format in BC Mode
o0 0 0 000 0 24 31 100000000 I nstruction Address
3240 63 PSW Format in EC Mode
System Controf 33
instruction becomes active (that is, the information
introduced into the current
over the system) at the completion of the interrup
tion or at the completion of the execution of the
instructiori, respectively. The interruption for
tion that changes the
the
the operation.
The figures below show
and EC modes.
Program Status Word Format in Be
Mode
The BC mode is specified by a zero in
tion 12. The following is a summary of the functions
Channel Masks 0-5: Bits
cannot cause an
one, a condition at the channel can cause an
o
Input/Output Mask
the
nels 6 and higher. When the bit is zero, these chan
nels cannot cause
one,
mask bits of the corresponding channels in control
register 2: when the channel-mask bit is zero, the
channel cannot cause
channel-mask bit is one, a condition at the channel
can cause an interruptiori.
External Mask (E): Bit 7 controls whether the
the external class. When the bit is zero, an external
interruption cannot occur. When the bit is one, an
external interruption is subject to the corresponding
external subclass-mask bits in control register
ciated with the subclass cannot cause an interrup
tion; when the subclass-mask bit is one, an interrup
tion in that subclass can occur.
Protection Key: Bits 8-11 form the
key. The key is matched with a key in storage when
ever information is stored, or whenever information
is fetched from a location that is protected against
fetching.
31
32 34 36
o
32
System Controf 33