Machine-Check Mask (M): Bit 13 controls whether
the CPU is enabled for interruption by machine­
check conditions. Its meaning is the same as in the
BC mode.
Wait State (W): When bit 14 is one, the CPU is in
the wait state. When bit 14 is zero, the CPU is in the
running state.
Problem State (P): When bit 15 is one, the CPU is
in the problem state. When bit 15 is zero, the CPU is
in the supervisor state.
Condition Code (CC): Bits 18 and 19 are the two
bits of the condition code.
Program Mask: Bits 20-23 are the four program­
mask bits. The meaning of these bits is the same as
that of bits 36-39 of the Be PSW. Instruction Address: Bits 40-63 form the logical
instruction address. This address designates the loca­
tion of the leftmost byte of the next instruction.
Bit positions 0, 2-4, 16-17, and 24-39 are unas­
signed. A specification exception is recognized when
these bit positions do not contain zeros.
Exceptions Associated with the PSW
Exceptions associated with the information in the
current PSW may be recognized when the informa­
tion is introduced into the PSW, or as part of the
execution of the next instruction.
Early Exception Recognition
For the following error conditions, a program inter­
ruption for specification exception occurs immedi­
ately after the PSW becomes active. • A one is introduced into an unassigned bit posi­
tion of the EC-mode PSW. • The EC mode is specified (PSW bit 12 is one)
in a CPU that does not have the EC facility
installed.
The interruption takes place regardless of whether
the wait state is specified. If the invalid PSW causes
the CPU to become enabled for a pending I/O, ex­
ternal, or machine-check interruption, the program
interruption is taken instead, and the pending inter­
ruption is subject to the mask bits of the new PSW introduced by the program interruption. If the EC
facility is not installed, bits 0-15 and 34-63 of the
invalid PSW are stored unchanged into the corre­
sponding bit positions of program,old PSW, and
the interruption code and instruction-length code are
stored into bit positions 16-33 of the program old PSW. When the execution of LOAD PSW or an inter­
ruption introduces a .PSW with one of the above
conditions, the instruction-length code is set to 0, and the newly introduced PSW, except for the inter­
ruption code and the instruction-length code in the
BC mode, is stored unmodified as the old PSW. When one of the above error conditions is intro­
duced by execution of SET SYSTEM MASK or STORE THEN OR SYSTEM MASK, the
instruction-length code is set to 2, and the instruc­
tion address is updated by two halfword locations.
The PSW containing the invalid value introduced
into the system-mask field is stored as the old PSW. When a PSW with one of the above error condi­
tions is introduced during initial program loading, the
loading sequence is not completed, and the load light
remains on.
Late Exception Recognition
For the following conditions, the exception is recog­
nized as part of the execution of the next instruction. • An instruction address is introduced in which PSW bit 63 is one (specification exception). • An access (addressing, protection, segment­
translation, page-translation, or translat\on­ specification) exception is associated with the
location designated by the instruction address
or the second or third halfword of the instruc­
tion starting at the designated address.
If the invalid PSW causes the CPU to be enabled
for a pending I/O, external, or machine-check inter­
ruption, the corresponding interruption occurs, and
the PSW invalidity is not recognized. Similarly, the
specification or access exception is not recognized in
a PSW specifying the wait state.
For specification, addressing, protection, and
translation-specification exceptions, the instruction­
length code (ILC) stored upon the program interrup­
tion is 1, 2, or 3, indicating the number of halfword
locations by which the instruction address has been
updated. Whether the ILC is 1, 2, or 3 is unpredicta­
ble. For segment-translation and page-translation
exceptions, the instruction address is not updated,
and the ILC is 1, 2, or 3, the indication being unpre­
dictable. In other respects, the current PSW, except
for the interruption code and the ILC in the BC
mode, is stored unmodified as the old PSW and con­
tains the invalid value causing the interruption. System Control 35

Programming Notes
The exeeution of LPSW, SSM, STNSM, and STOSM is on an addressing or protection excep­
tion, and hence the program old PSW provides in­
formation concerning the program causing the ex­
ception.
When the first halfword of an instruction can be
fetched but an access exception is recognized on
fetching the second or third halfword, the
instruction-length code is not necessarily related to
the operation code. I If the new PSW introduced by an interruption
contains a format error, a series of interruptions
occurs. See the section "Priority of Interruptions" in
the chapter "Interruptions."
Control Registers
The control registers provide a means for maintain­
ing and manipulating control information that re­
sides outside the PSW. The addressing structure provides for sixteen 32-
bit registers for control purposes. These registers are
not part of addressable storage. The instruction LOAD CONTROL provides a means for loading
control information from main storage into control
registers, whereas STORE CONTROL permits in­
formation to be transferred from control registers to
main storage. These instructions operate in a manner
similar to LOAD MULTIPLE and STORE MULTI­
PLE. One or more specific bit positions in control regis­
ters are assigned to each facility such regis­
ter space. When the facility and the associated reg-
36 System/370 Principles of Operation ister positions are installed, the bit performs the indi­
cated control function, and STORE CONTROL returns the information placed in the register posi­
tion by LOAD CONTROL or on reset. When STORE CONTROL is executed, the value corre­
sponding to the unassigned register positions is un­
predictable.
At the time the registers are loaded, the informa­
tion is not checked for exceptions, such as invalid
segment-size or page-size code or an address desig­
nating an unavailable or a protected location. The
validity of the information is checked and the excep­
tions, if any, are indicated at the time the informa­
tion is used. Only the general structure of control registers is
described here; a definition of the meaning of regis­
ter pOSitions appears with the description of the fa­
cility with which the register position is associated. A
summary of control register allocation appears in the
table "Assignment of Control Register Fields." This
table shows the facility with which the field is associ­
ated and the initial value placed in the field upon
execution of reset.
Programming Note
To ensure that presently written programs run if and
when new facilities using additional control register
positions are installed, only zeros should be loaded
in unassigned control register positions. Similarly,
although on some CPUs STORE CONTROL may
provide zeros in the bit positions corresponding to
the unassigned register positions, the program should
not depend on such zeros being provided.