Extended Control Mode: Bit 12 controls the format
of the PSW and the mode of operation of the CPU. When the bit is zero, the PSW format and the CPU operation are as defined for the basic control (BC)
mode. When the bit is one, the extended control
(EC) mode is specified.
Machine-,Check Mask (M): Bit 13 controls whether
the CPU is enabled for interruption by machine­
check conditions. When the bit is zero, a machine­
check int1erruption cannot occur. When the bit is
one, machine-check interruptions due to system
damage and instruction-processing damage are per­
mitted, and interruptions due to other machine­
check conditions are subject to the subclass-mask
bits in control register 14.
Wait St.,te (W): When bit 14 is one, the CPU is in
the wait state. When bit 14 is zero, the CPU is in the
running state.
Problem State (P): When bit 15 is one, the CPU is
in the problem state. When bit 15 is zero, the CPU is
in the supervisor state. Inte"uptilfJn Code: Bits 16-31 in the old PSW stored on a program, supervisor-call, external, or I/O interruption identify the cause of the interrup­
tion. When a new PSW is introduced, the contents of
this field are ignored. Instructim.-ungth Code (lLC): The code in bit
positions 32 and 33 indicates the length of the last­
interpreted instruction when a program or
supervisor-call interruption occurs or when
BRANCH AND LINK is executed. When a new PSW is introduced, the contents of this field are
ignored.
Condition Code (CC): Bits 34 and 35 are the two
bits of the condition code.
Program Mask: Bits 36-39 are the four program­
mask bits" Each bit is associated with a program
exception, as follows:
Program
Mask Bit
36
37
38
39
Program Exception
Fixed-point overflow Decimal overflow Exponent underflow Significance
When the mask bit is one, the exception results in
an interruption. When the mask bit is zero, no inter­
ruption occurs. The significance-mask bit also deter-
34 System/370 Principles of Operation mines the manner in which floating-point addition
and subtraction are completed.
Instruction Address: Bits 40-63 form the instruction
address. This address designates the location of the
leftmost byte of the next instruction.
Program Status Word Format in Ee
Mode
The EC mode is specified by a one in PSW bit posi­
tion 12. The following is a summary of the functions
of the PSW fields:
Program-Event-Recording Mask (R): Bit 1 controls
whether the CPU is enabled for interruption by pro­
gram events associated with the program-event­
recording facility. When the bit is zero, no program
event can cause an interruption. When the bit is one,
interruptions are permitted subject to the event­
mask bits in control register 9.
Translation Mode (T): Bit 5 controls whether im­
plicit translation of storage addresses by use of seg­
ment and page tables takes place. When the bit is
zero, storage addresses are not translated. When the
bit is one, the dynamic-address-translation mecha­
nism is invoked.
Input / Output Mask (10): Bit 6 controls whether
the CPU is enabled for I/O interruptions. When the
bit is zero, an I/O interruption cannot occur. When
the bit is one, I/O interruptions are subject to the
channel-mask bits in control register 2: when the
channel-mask bit is zero, the channel cannot cause
an interruption; when the channel-mask bit is one, a
condition at the channel can cause an interruption.
External Mask (E): Bit 7 controls whether the CPU is enabled for interruption by conditions included in
the external class. Its meaning is the same as in the
BC mode.
Protection Key: Bits 8-11 form the CPU protection
key. The key is matched against a key in storage
whenever information is stored, or whenever informa­
tion is fetched from a location that is protected
against fetching.
Extended-Control Mode: Bit 12 controls the format
of the PSW and the mode of operation of the CPU. When the bit is zero, the PSW format and the CPU operation are as defined for the basic-control (BC)
mode. When the bit is one, the extended-control
(EC) mode is specified.

Machine-Check Mask (M): Bit 13 controls whether
the CPU is enabled for interruption by machine­
check conditions. Its meaning is the same as in the
BC mode.
Wait State (W): When bit 14 is one, the CPU is in
the wait state. When bit 14 is zero, the CPU is in the
running state.
Problem State (P): When bit 15 is one, the CPU is
in the problem state. When bit 15 is zero, the CPU is
in the supervisor state.
Condition Code (CC): Bits 18 and 19 are the two
bits of the condition code.
Program Mask: Bits 20-23 are the four program­
mask bits. The meaning of these bits is the same as
that of bits 36-39 of the Be PSW. Instruction Address: Bits 40-63 form the logical
instruction address. This address designates the loca­
tion of the leftmost byte of the next instruction.
Bit positions 0, 2-4, 16-17, and 24-39 are unas­
signed. A specification exception is recognized when
these bit positions do not contain zeros.
Exceptions Associated with the PSW
Exceptions associated with the information in the
current PSW may be recognized when the informa­
tion is introduced into the PSW, or as part of the
execution of the next instruction.
Early Exception Recognition
For the following error conditions, a program inter­
ruption for specification exception occurs immedi­
ately after the PSW becomes active. • A one is introduced into an unassigned bit posi­
tion of the EC-mode PSW. • The EC mode is specified (PSW bit 12 is one)
in a CPU that does not have the EC facility
installed.
The interruption takes place regardless of whether
the wait state is specified. If the invalid PSW causes
the CPU to become enabled for a pending I/O, ex­
ternal, or machine-check interruption, the program
interruption is taken instead, and the pending inter­
ruption is subject to the mask bits of the new PSW introduced by the program interruption. If the EC
facility is not installed, bits 0-15 and 34-63 of the
invalid PSW are stored unchanged into the corre­
sponding bit positions of program,old PSW, and
the interruption code and instruction-length code are
stored into bit positions 16-33 of the program old PSW. When the execution of LOAD PSW or an inter­
ruption introduces a .PSW with one of the above
conditions, the instruction-length code is set to 0, and the newly introduced PSW, except for the inter­
ruption code and the instruction-length code in the
BC mode, is stored unmodified as the old PSW. When one of the above error conditions is intro­
duced by execution of SET SYSTEM MASK or STORE THEN OR SYSTEM MASK, the
instruction-length code is set to 2, and the instruc­
tion address is updated by two halfword locations.
The PSW containing the invalid value introduced
into the system-mask field is stored as the old PSW. When a PSW with one of the above error condi­
tions is introduced during initial program loading, the
loading sequence is not completed, and the load light
remains on.
Late Exception Recognition
For the following conditions, the exception is recog­
nized as part of the execution of the next instruction. • An instruction address is introduced in which PSW bit 63 is one (specification exception). • An access (addressing, protection, segment­
translation, page-translation, or translat\on­ specification) exception is associated with the
location designated by the instruction address
or the second or third halfword of the instruc­
tion starting at the designated address.
If the invalid PSW causes the CPU to be enabled
for a pending I/O, external, or machine-check inter­
ruption, the corresponding interruption occurs, and
the PSW invalidity is not recognized. Similarly, the
specification or access exception is not recognized in
a PSW specifying the wait state.
For specification, addressing, protection, and
translation-specification exceptions, the instruction­
length code (ILC) stored upon the program interrup­
tion is 1, 2, or 3, indicating the number of halfword
locations by which the instruction address has been
updated. Whether the ILC is 1, 2, or 3 is unpredicta­
ble. For segment-translation and page-translation
exceptions, the instruction address is not updated,
and the ILC is 1, 2, or 3, the indication being unpre­
dictable. In other respects, the current PSW, except
for the interruption code and the ILC in the BC
mode, is stored unmodified as the old PSW and con­
tains the invalid value causing the interruption. System Control 35