Programming Notes
The exeeution of LPSW, SSM, STNSM, and STOSM is on an addressing or protection excep­
tion, and hence the program old PSW provides in­
formation concerning the program causing the ex­
ception.
When the first halfword of an instruction can be
fetched but an access exception is recognized on
fetching the second or third halfword, the
instruction-length code is not necessarily related to
the operation code. I If the new PSW introduced by an interruption
contains a format error, a series of interruptions
occurs. See the section "Priority of Interruptions" in
the chapter "Interruptions."
Control Registers
The control registers provide a means for maintain­
ing and manipulating control information that re­
sides outside the PSW. The addressing structure provides for sixteen 32-
bit registers for control purposes. These registers are
not part of addressable storage. The instruction LOAD CONTROL provides a means for loading
control information from main storage into control
registers, whereas STORE CONTROL permits in­
formation to be transferred from control registers to
main storage. These instructions operate in a manner
similar to LOAD MULTIPLE and STORE MULTI­
PLE. One or more specific bit positions in control regis­
ters are assigned to each facility such regis­
ter space. When the facility and the associated reg-
36 System/370 Principles of Operation ister positions are installed, the bit performs the indi­
cated control function, and STORE CONTROL returns the information placed in the register posi­
tion by LOAD CONTROL or on reset. When STORE CONTROL is executed, the value corre­
sponding to the unassigned register positions is un­
predictable.
At the time the registers are loaded, the informa­
tion is not checked for exceptions, such as invalid
segment-size or page-size code or an address desig­
nating an unavailable or a protected location. The
validity of the information is checked and the excep­
tions, if any, are indicated at the time the informa­
tion is used. Only the general structure of control registers is
described here; a definition of the meaning of regis­
ter pOSitions appears with the description of the fa­
cility with which the register position is associated. A
summary of control register allocation appears in the
table "Assignment of Control Register Fields." This
table shows the facility with which the field is associ­
ated and the initial value placed in the field upon
execution of reset.
Programming Note
To ensure that presently written programs run if and
when new facilities using additional control register
positions are installed, only zeros should be loaded
in unassigned control register positions. Similarly,
although on some CPUs STORE CONTROL may
provide zeros in the bit positions corresponding to
the unassigned register positions, the program should
not depend on such zeros being provided.

Word
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
2
8
9
9
9
9
9
10
11
14
14
14
14
14
14
14
14
14
15
Bits 0 2
8-9
10
11-12
16
17
18
19
20
21
24
25
26
0-7
8-25
0-31
16-31 0 2
3
16-31
8-31
8-31 0 2
4
5
6
7
8
9
8-28
Explanation:
Name of field
Block-Multiplexing Control SSM-Suppression Control TOD Clock Sync Control
Page-Size Control
Unassigned, must be zero Segment-Size Control
Malfunction-Alert Mask
Emergency-Signal Mask 1 "',' , External-Call Mask .. TOD-Clock-Sync-Check Mask
Clock-Comparator Mask
CPU-Timer Mask Interval-Timer Mask
Interrupt-Key Mask
External-Signal Mask Se£ment-Table Length Segment"Table Address
Channel Masks
Monitor Masks
Successful-Branching Event Mask
Instruction-fetching-Event Mask
Storage-Alteration-Event Mask
GR-Alteration-Event Mask
PER 1 General Register Masks
PER Starting Address
PER Ending Address
Check-Stop Control
Synchronous-MCE L
2
Control
I/O-Extended-Logout Control
Recovery-Report Mask
Degradation-Report Mask
External-Damage-Report Mask
Warning Mask
Asynchronous-MCEL Control
Asynchronous-Fixed-Log Control
MCEL Address
The fields not listed are unassigned.
Associated With
Block-Multiplexing SSM Suppression
Multiprocessing
Dynamic Addr. Translation
Dynamic Addr. Translation
Dynamic Addr. Translation
Multiprocessing
Multiprocessing
Multiprocessing
Multiprocessing
Clock Comparator
CPU Timer
Interval Timer
Interrupt Key
External Signal Dynamic Addr. Translation
Dynamic Addr. Translation
Channels
Monitoring
Program-Event Recording
Program-Event Recording
Program-Event Recording
Program-Event Recording
Program-Event Recording
Program-Event Recording
Program-Event Recording
Machine-Check Handling
Machine-Check Handling I/O Extended Logout
Machine-Check Handling
Machine-Check Handling
Machine-Check Handling
Machine-Check Handling
Machine-Check Handling
Machine-Check Handling
Machine-Check Handling
Except for bit 10 of control register 0, the initial value of unassigned register positions is unpredictable.
1 PER means program-event recording.
2 MCEL means machine-check extended logout.
3 Bit 22 is set to one, with all other bits set to zero, thus yielding a decimal byte address of 512.
Assignment of Control Registel' Fields Initial Value
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
o
1
o
o
o
o
o
o
512
3
System Control 37