When a store access is prohibited because of pro­
tection, the contents of the protected location re­
main unchanged. On fetching, the protected informa­
tion is not loaded into an addressable register,
moved to another storage location, or provided to an I/O device.
The protection system is always active, regardless
of whether the CPU is in the problem or supervisor
state and regardless of the type of CPU instruction
or channel command word being executed.
Accesses Protected
All main-storage accesses to locations that are ex­ plicitly designated by the program and that are used
by the CPU or channel to store or fetch information
are subject to protection.
Protection is not appHed to accesses that are im­
plicitly made by the CPU or channel for such se­
quences as interruptions, updating the interval timer,
logout, dynamic address translation, fetching the
CAW during execution of an I/O instruction, storing
the CSW by an I/O instruction or interruption, stor­ ing channel identification during execution of STORE CHANNEL ID, and the initial-pro gram­
loading and store-status functions. Similarly, protec­
tion does not apply to accesses initiated via the sys­
tem console for entering or displaying information.
However, when the program explicitly designates
these locations, they are subject to protection.
Monitoring
The monitoring facility provides the capability for
passing control to a monitoring program when se­
lected indicators are reached in the monitored pro­
gram. The indicators are MONITOR CALL instruc­
tions implanted in the monitored program. When
executed, these instructions cause a program inter­
ruption for monitoring to take place, provided an
interruption is allowed for the monitor class speci­
fied by the instruction. Along with the interruption,
the monitor class number and a monitor code are
stored for subsequent use by the monitoring pro­
gram.
The monitoring facility includes the instruction MONITOR CALL, which designates one of 16
monitoring classes, together with a set of 16 monitor
masks in a control register. One mask bit is associat­
ed with each class. The execution of the instruction
causes a program interruption when the monitor­
mask bit for the class specified in the instruction is
one. I The monitoring facmty is available in both the BC
and EC modes.
The monitor-mask bits are in bit positions 16-31
of control register 8.
Control Register 8:
Monitor Masks
o 16
The mask bits, 16-31, correspond to monitor
classes 0-15, respectively. Any number of monitor­
mask bits may be on at anyone time; together they
specify the classes of monitor events that are moni­
tored at that time. The mask bits are initialized to
zero.
31
When a MONITOR CALL instruction is inter­
preted for execetion and the corresponding monitor­
mask bit is one, a program interruption for monitor­
ing occurs. The cause of the interruption is identified
by setting bit 9 of the interruption code to one, and
by the information placed at locations 148-149 and
156-159 of main storage. The format of the informa­
tion placed at locations 148-149 and 156-159 is the
same in BC and EC modes and is as follows:
Locations 148-149:
Monitor 00000000 Class No.
o 8
Locations 156-159: I L_o_o_o_o __ _________ M __ on_i_to_r_C_o_de __________ o 8 31
The contents of bit positions 8-15 of MONITOR CALL are placed at location 149 and constitute the
monitor class number. The address specified by the
Bl and Dl fields of the instruction forms the monitor
code, which is placed at locations 157-159. Zeros
are placed at locations 148 and 156.
Program..;Event Recording
The purpose of the program-event-recording (PER) facility is to assist in debugging programs. It permits
the program to be alerted to the following events: • Successful execution of a branch instruction. • Alteration of the contents of designated general
registers. • Fetching of an instruction from designated
main-storage locations. • Alteration of the contents of designated main­
storage locations.
The program has control over the conditions that
are considered eventf- recording purposes and
can specify selectively one or more events to be
monitored. The information concerning a program
System Control 39

event is provided to the program by means of a pro­
gram interruption, with the cause of the interruption
being idemtified in the interruption code.
Control Register Allocation
The information for controlling program-event re­
cording resides in control registers 9, 10, and 11 and
consists of the following fields:
Control Register 9: a Genera,-Re9;ste3 o 4 16 31
Control Register 10: __ __________ S_ta_rt_in_g_A_d_d_re_s_s ________ o 8 31
Control Register 11: r--I Ending Address o 8 31
PER El'l!nt Mmks: Bits 0-3 of control register 9
specify which events are monitored. The bits are
assigned as follows:
Bit 0: Successful-Branching Event
Bit 1: Instruction-Fetching Event
Bit 2: Storage-Alteration Event
Bit 3: General-Register-Alteration Event
Bits 0··3, when ones, specify that the correspond­
ing events are monitored. When the bit is zero, the
event is not monitored.
PER General-Register Masks: Bits 16-31 of control
register 9 specify which general registers are moni­
tored for alteration of their contents. The 16 bits, in
the order of ascending bit numbers, are made to
correspond one for one with the 16 registers, in the
order of ascending addresses. When the bit is one,
the register is included in monitoring for alteration;
if zero, the register is not monitored.
PER Starling Address: Bits 8-31 of control register 10 form :an address that designates the beginning of
the monitored main-storage area.
PER Elrding Address: Bits 8-31 of control register
11 form :an address that designates the end of the 40 System/370 Principles of Operation monitored main-storage area.
Programming Note
Most models operate at reduced performance while
monitoring for program events. In order to ensure
that CPU performance is not degraded due to the
operation of the program-event-recording facility,
programs that do not utilize program-event record­
ing should disable program-event recording by set­
ting the PER mask in the EC-mode PSW to zero. No
degradation due to program-event recording occurs
in the BC mode or when the PER mask in the EC­
mode PSW is zero. Disabling of program-event re­
cording in the EC mode by means of the masks and
addresses in control registers 9-11 does not neces­
sarily assure avoidance of performance degradation
due to the use of the facility.
Operation
Program-event recording (PER) is available only in
the EC mode and is under control of PSW bit 1, the PER mask; when the mask is zero, no program event
can cause an interruption; whel1 the mask is one, a
monitored event, as specified by the contents of
control registers 9, 10, and 11, causes an interrup­
tion. In BC mode the PER mask has, in effect, a
value of zero, and program-event recording is dis­
abled.
An interruption due to a program event is taken
,after the execution of the instruction responsible for
the event. The occurrence of the event does not
affect the execution of the instruction, which may be
either completed, terminated, suppressed, or nulli­
fied.
A program-event condition cannot be kept pend­
ing. When the CPU is disabled for a particular pro­
gram event at the time it occurs, either by the mask
in the PSW or by the masks in control register 9, the
interruption condition is lost.
A change to the PER mask in the PSW or to the PER control fields in control registers 9, 10, and 11
affects program-event recording starting with the
execution of the immediately following instruction.
When the CPU is enabled for some program event
and an instruction causes the CPU to be disabled for
that particular event, the event causes an interrup­
tion if it occurs during the execution of the instruc­
tion.
When LOAD PSW or SUPERVISOR CALL
causes a PER condition and at the same time
changes CPU operation from EC mode to BC mode,
the PER interruption is taken with the old PSW specifying BC mode and with the interruption code
stored in the old PSW. The additional information