Execution of the initial-program-reset function is
initiated in a CPU by one of the following:
1. On a model that does not have the store-status
facility installed, by activating the system-reset
key on that CPU, with the enable-system-clear
key in the normal position.
2. By activating the load key on that CPU, with
the enable-system-clear key in the normal posi­
tion. (The initial-pro gram-reset function is im­
mediately followed by the initial-pro gram­
loading operation.)
3. When the CPU accepts the initial-pro gram­
reset order specified by a SIGNAL PRO­ CESSOR instruction addressing this CPU. System-Clear Reset
System-clear reset causes initial CPU reset to be
performed, causes I/O system reset to be performed
in all channels configured to the CPU, and causes
the contents to be set to zeros with valid checking­
block code in that part of main storage and of keys
in storage that is configured to the CPU. Additional­
ly, the checking-block code of the contents of gener­
al registers and floating-point registers is made valid.
In most models the contents of the registers are
cleared to zeros, but in some the contents may be
left unchanged except for making the checking-block
code valid.
See the table "Summary of Reset Action" for a
detailed description of the effect of the reset on oth­
er parts of the system.
Execution of the system-clear-reset function is
initiated in a CPU by one of the following:
1. By activating the system-reset key on that CPU, with the enable-system-clear key in the
clear position.
2. By activating the load key on that CPU, with
the enable-system-clear key in the clear posi­
tion. (The system-clear function is immediately
followed by the initial-pro gram-loading opera­
tion.)
3. By performing either of the above on any other
configured CPU in a multiprocessing system.
Programming Notes
In order for the CPU-reset and initial-CPU-reset
operations not to affect the contents of fields that
are to be left unchanged, the CPU must not be exe­
cuting instructions and must be disabled for all inter­
ruptions at the time of the reset. Except for the oper­
ation of the interval timer, CPU timer, and clock
comparator and for the possibility of taking a
machine-check interruption, all CPU activity can be
quiesced by placing the CPU in the wait state and by
disabling it for I/O and external interruptions. In
order to avoid the possibility of causing a CPU reset
at the time the timing facilities are being updated or
a machine-check interruption occurs, the CPU must
be in the stopped state.
Resetting of the CPU does not affect the value
and operation of the time-of-day clock.
System-clear reset causes all bit positions of the
interval timer to be cleared to zeros.
The conditions under which the CPU enters the
check-stop state are model-dependent and include
malfunctions that preclude the completion of the
current operation. Hence, in general, when CPU reset or initial CPU reset is executed in a CPU that
is in the check-stop state, the contents of the PSW, addressable registers, and storage locations, includ­
ing the keys, accessed at the time of the error are not
reliable. Power-On Reset
The power-on-reset function for a component of the
system is performed as part of the power-on se­
quence for that component.
The power-on sequences for the TOD clock, main
storage, and channels may be included as part of the CPU power-on sequence, or the power-on sequence
for these units may be initiated separately. The fol­
lowing sections describe the power-on resets for the CPU, TOD clock, and main storage. See also "I/O Operations" and the appropriate Systems Reference
Library (SRL) or System Library (SL) publication
for channels, control units, and I/O devices. CPU Power-On Reset: The power-on reset causes
initial CPU reset to be performed and causes I/O system reset to be performed in all channels config:­ ured to the CPU. The checking-block code on the
contents of general registers and floating-point regis­
ters is made valid. In most models the contents are
cleared to zero, but in some models the contents
may be left unpredictable except for the checking­
block code. TOD Clock Power-On Reset: The power-on reset
causes the value of the time-of -day clock to be set to
zero and causes the clock to enter the not-set state.
Main-Storage Power-On Reset: For volatile main
storage (one that does not preserve its contents
when power is down) and for keys in storage,
power-on reset causes valid checking-block code to
be placed in these fields. In most models the con­
tents are cleared to zeros, but in some models the
contents may be left unpredictable except for the
checking-block code. The contents of nonvolatile System Control 53

main storage, including the checking-block code,
remain unchanged.
Store Status
The store-status facility includes the following:
1. A ehange to the operation of the system-reset
key when the enable-system-clear key is in the
normal position. With the store-status facility
installed, pressing the system-reset key causes
a program reset; without this facility, initial
program reset is performed.
2. An operator-initiated store-status function.
The store-status operation consists in placing the
contents of the current PSW and the program­
addressable registers in permanently assigned loca­
tions within the first 512 bytes of main storage. In
the BC mode, the instruction-length code in the PSW is unpredictable, and an interruption code of
zero is stored. The information provided for control
register positions not associated with an installed
facility is unpredictable. If the CPU timer, clock
comparator, prefix register, or floating-point facility
is not installed, the contents of the corresponding
locations in main storage remain unchanged.
The word beginning at absolute storage address
268 is reserved for storing additional status as re­
quired by certain model-dependent If no
feature requiring this field is installed, the contents
of the field remain unchanged upon execution of the
store-status function.
The following table lists the fields that are stored,
their length, and their location in main storage.
Length in Absolute
Field Bytes Address
1 CPU timer 8 216
Clock comparator 8 224
Current PSW 8 256 Prefix 4 264
Model-dependent feature 4 268 F-P registers 0-6 32 352
General registers 0-15 64 384
Control registers 0-15 64 448
Explanation:
1 Decimal iEiddress of the first byte of the field in absolute main
storage. Permanently Assigned Storage for Store Status
The contents of the registers are not changed. If
an error is encountered during the operation, the CPU enters the check-stop state.
The store-status operation can be initiated by the
operator on the system console. The operator con­
trols andl the procedure for initiating the function
may differ among models and are described in the System Library (SL) publication for the model. In a
54 Sysh:m/370 Principles of Operation
multiprocessing system, the store-status operation
can also be initiated at the addressed CPU by execu­
ting SIGNAL PROCESSOR, specifying the stop­
and-store-status order.
Initial Program Loading
Initial program loading (IPL) is provided for the
initiation of processing when the contents of main
storage or of the pSW are not suitable for process-
ing.
Initial program loading is initiated manually by
selecting an input device with the load-unit-address
switches and then pressing the load key. Pressing the
load key causes a system-clear or an initial-program­
reset operation to be performed on the CPU, as de­
termined by the setting of the enable-system-clear
key. Subsequently, a read operation is initiated from
the selected input device.
The read operation is performed as if a START I/O instruction were executed that specified the
device addressed by the load-unit-address switches
and used a channel address word ( CAW) containing
a protection key of zero and a channel command
word (CCW) address of 0. The address set up on
the load-unit-address switches provides the 12 low­
order bits of the I/O address; zeros are implied for
the high-order address bits. Although the location of
the first CCW to be executed is specified as 0, the
first CCW actually executed is an implied CCW,
containing, in effect, a read command with the mod­
ifier bits set to zero, a data address of 0, a byte
count of 24, the chain-command flag on, the
suppress-incorrect-Iength-indication flag on, the
chain-data flag off, the skip flag off, and the
program-controlled-interruption (PCI) flag off. The
CCW fetched, as a result of command chaining,
from location 8 or 16, as well as any subsequent
CCW in the IPL sequence, is interpreted the same as
a CCW in any I/O operation, with the exception
that the PCI flag is ignored.
When the I/O device provides channel-end status
for the last operation of the IPL chain and no excep­
tional conditions are detected in the operation, a
new PSW is obtained from locations 0-7. When this PSW specifies the BC mode, the I/O address that
was used for the IPL operation is stored at locations
2 and 3; when the EC mode is specified, the I/O address is stored at locations 186-187, and zeros are
stored at location 185. The load indicator is turned
off, and CPU operation proceeds under the control
of the new PSW. When channel-end status for the IPL operation is
presented, either separate from or along with device­
end status, no I/O interruption condition is generat­
ed. Similarly, any PCI flags specified by the pro-