I nterruption Action.
Source Identification Enabling and Disabling Instruction-Length Code Zero ILC .
Contents I LC on Instruction Fetch Exceptions. Point of Interruption Instruction Execution .
Types of Ending
Execution of I nterruptible Instructions Machine-Check Interruption Program Interruption Program I nterruption Conditions
Operation Exception Privileged-Operation Exception
Execute Exception . Protection Exception
Addressing Exception
Specification Exception
Data Exception . Fixed-Point-Overflow Exception
Fixed-Point-Divide Exception Decimal-Overflow Exception . Decimal-Divide Exception . Exponent-Overflow Exception
Exponent-Underflow Exception
Significance Exception . Floating-Point-Divide Exception
Segment-Translation Exception Page-Translation Exception
Translation-Specification Exception Special-Operation Exception
Monitor Event Program Event
Recognition of Access Exceptions Handling of. Multiple Program-I nterruption Conditions Supervisor-Call Interruption External Interruption Interval Timer Interrupt Key External Signal Malfunction Alert Emergency Signal External Call .
Time-of-Day Clock Sync Check Clock Comparator . CPU Timer Input/Output Interruption. Restart Priority of Interruptions Assigned Main-Storage Locations Real Main Storage Absolute Main Storage . Page of GA22-70004 Revised September 1, 1975
By TNL: GN22-0498
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Interruptions
Interruptions 69
The interruption system permits the CPU to change
its stat.e as a result of conditions external to the sys­
tem, within the system, or within the CPU itself. To
permit fast response to conditions of high priority
and immediate recognition of the type of condition,
interrUlption conditions are grouped into six classes:
input-output, external, program, supervisor call, ma­
chine check, and restart.
Interruption Action
An interruption consists in storing the current PSW as an old PSW, storing further detail information
identifying the cause of the interruption, and fetch­
ing a new PSW. Processing resumes as specified by
the new PSW. The old PSW stored on an interruption normally
contailtls the address of the instruction that would
have been executed next had the interruption not
occurred, thus permitting resumption of the inter­
rupted program. For program and supervisor-call
interruptions, the information stored also contains a
code that identifies the length of the last-executed
instruction, thus permitting the program to respond
to the cause of the interruption. In the case of some
program conditions for which the execution of the
instruction causing the interruption normally is re­
sumed, the instruction address directly identifies the
instruction last executed.
Except for restart, an interruption can take place
only when the CPU is in the operating state. The
restart interruption can occur with the CPU either
stopped or operating. The details of source identification, location de­
termination, and instruction execution are explained
in later sections and are summarized in the table
"Intenruption Action." Programming Note See the section "Program Status Word" in the chap­
ter "System Control" for details as to when the new PSW introduced by an interruption is checked for
format errors. Sour,ce Identification
The six classes of interruptions (I/O, external, pro­
gram, supervisor call, machine check, and restart)
are distinguished by the storage locations at which
the old PSW is stored and from which the new PSW is fetched. For most classes, the causes are further
identified by an interruption code and, for some
classes:, by additional information placed in main
storage during the interruption. For I/O, external,
supervisor-call, and program interruptions, the inter­
ruption code comprises 16 bits and is placed in the
old PSW when the old PSW specifies the BC mode 70 System/370 Principles of Operation
and in separate main-storage locations when the EC
mode is specified.
For I/O interruptions, additional information is
provided by the contents of the channel status word (CSW) stored at location 64, and further informa­
tion may be provided by the limited channel logout
stored at location 176 and by the I/O extended log­
out.
For program interruptions, additional information
may be provided in the form of the translation­
exception address, monitor-class number and moni­
tor code, and PER code and PER address stored at
locations 144-159.
For machine-check interruptions, the interruption
code comprises 64 bits and is placed in main storage
at location 232. Additional information for identify­
ing the cause of the interruption and for recovering
the state of the CPU may be provided by the con­
tents of the logout and save areas.
The assignment and format of the permanently
allocated storage locations is shown in the table
"Permanently Assigned Storage Locations" at the
end of this chapter.
Enabling and Disabling
The CPU may be enabled or disabled for all I/O, external, and machine-check interruptions and for
some program interruptions. When the CPU is ena­
bled for a class of interruptions, these interruptions
can take place. When the CPU is disabled, the condi­
tions that cause I/O interruptions remain pending,
and the disallowed program-interruption conditions
are ignored, except that some causes are indicated
also by the setting of the condition code. External
and machine-check conditions, depending on the
type, are ignored or remain pending.
Program interruptions for which mask bits are not
provided, as well as the supervisor-call and restart
interruptions, are always taken.
Whether the CPU is enabled or disabled for a
particular type of interruption is controlled by mask
bits in the current PSW and in control registers. The
setting of the mask bits may disallow all interrup­
tions within the class or may selectively allow inter­
ruptions for particular causes. This control is pro­
vided by assigning a mask bit in the PSW to a partic­
ular cause, such as in the case of the four maskable
program interruption conditions, or by providing a
hierarchy of masks, where a mask in the PSW con­
trols all interruptions within a type, and masks in
control registers provide more detailed control over
the sources.
When the mask bit is one, the CPU is enabled for
the corresponding interruptions. When the mask bit
is zero, these interruptions are disallowed. Interrup-
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