tions that are controlled by a hierarchy of masks are
allowed only when all mask bits in the hierarchy are
ones.
Programming Note
Mask bits in thePSW provide a means of disabling
all maskable interruptions; thus, subsequent inter
ruptions can be disallowed by the newPSW intro
duced by an interruption. Furthermore, the mask
bits can be used to establish a hierarchy of interrup
tion priorities, where a condition in one class can
interrupt the program handling a condition in anoth
er class but not vice versa. To prevent an
interruption-handling routine from being interrupted
before the necessary housekeeping steps are per
formed, the newPSW must disable the CPU for
further interruptions within the same class or within
a class of lower priority.
Since the mask bits in control registers are not
changed as part of the interruption procedure, these
masks cannot be used to prevent an interruption
immediately after a previous interruption in the same
class. The mask bits in control registers provide a
means for selectively enabling theCPU for some
sources and disabling it for others within the same
class.
Instruction-Length Code
The instruction-length codeOLC) occupies two bit
positions and provides the length of the last instruc
tion executed. It permits identifying the instruction
causing the interruption when the instruction address
in the oldPSW designates the next sequential in
struction. The ILC is provided also by the BRANCH
AND LINK instructions.
In an oldPSW specifying the BC mode, the
instruction-length code is stored in bit positions 32
and 33. It is meaningful, however, only after a pro
gram or supervisor-call interruption. ForI/O, exter
nal, machine-check, and restart interruptions, the
code does not indicate the length of the last
executed instruction and is unpredictable. Similarly,
the ILC is unpredictable in thePSW stored during
execution of the store-status function and when thePSW is displayed.
When the oldPSW specifies the EC mode, the
instruction-length code for supervisor-call and pro
gram interruptions is stored in bit positions 5 and 6
of the bytes at locations 137 and 141, respectively.
ForI/O, external, machine-check, and restart inter
ruptions the code is not stored.
For supervisor-call and program interruptions, a
nonzero instruction-length code identifies in half
words the length of the instruction that was last ex
ecuted. Whenever an instruction is executed by
means of EXECUTE, instruction-length code 2 is
set to indicate the length of EXECUTE and not that
of the subject instruction.
The value of a nonzero instruction-length code is
related to the leftmost two bits of the instruction.
The value is not contingent on whether the operation
code is assigned or on whether the instruction is
installed. The following table summarizes the mean
ing of the instruction-length code:ILC Decimal Binary Instruction Bits 0-1 I nstruction Length 0 00 Not available 01 00 One halfword 2 10 01 Two halfwords 2 10 10 Two halfwords 3 11 11 Three halfwords Zero ILC
Instruction-length code0, after a program interrup
tion, indicates that the location of the instruction
causing the interruption is not made available to the
program. Instruction-length code° occurs only in
the following cases:
1. When a specification exception is recognized
that is due to aPSW format error, other than
one due to an odd instruction address, and the
invalidPSW has been introduced by LOAD PSW or an interruption. In the case of LOAD PSW, the address of the instruction has been
replaced by the newPSW. When the invalid PSW is introduced by an interruption, the for
mat error cannot be attributed to an instruc
tion.
2.On some models, when an addressing exception
(excluding those detected during implicit refer
ences to dynamic-address-translation-table
entries) or a protection exception is recognized
during a store-type reference. In these cases
the interruption due to the exception is de
layed, the length of time or number of instruc
tions of the delay being unpredictable. Neither
the location of the instruction causing the ex
ception nor the length of the last-executed in
struction is made available to the program.
When the newPSW introduced by LOAD PSW or a supervisor-call interruption has a format error,
Interruptions 71
allowed only when all mask bits in the hierarchy are
ones.
Programming Note
Mask bits in the
all maskable interruptions; thus, subsequent inter
ruptions can be disallowed by the new
duced by an interruption. Furthermore, the mask
bits can be used to establish a hierarchy of interrup
tion priorities, where a condition in one class can
interrupt the program handling a condition in anoth
er class but not vice versa. To prevent an
interruption-handling routine from being interrupted
before the necessary housekeeping steps are per
formed, the new
further interruptions within the same class or within
a class of lower priority.
Since the mask bits in control registers are not
changed as part of the interruption procedure, these
masks cannot be used to prevent an interruption
immediately after a previous interruption in the same
class. The mask bits in control registers provide a
means for selectively enabling the
sources and disabling it for others within the same
class.
Instruction-Length Code
The instruction-length code
positions and provides the length of the last instruc
tion executed. It permits identifying the instruction
causing the interruption when the instruction address
in the old
struction. The ILC is provided also by the BRANCH
AND LINK instructions.
In an old
instruction-length code is stored in bit positions 32
and 33. It is meaningful, however, only after a pro
gram or supervisor-call interruption. For
nal, machine-check, and restart interruptions, the
code does not indicate the length of the last
executed instruction and is unpredictable. Similarly,
the ILC is unpredictable in the
execution of the store-status function and when the
When the old
instruction-length code for supervisor-call and pro
gram interruptions is stored in bit positions 5 and 6
of the bytes at locations 137 and 141, respectively.
For
ruptions the code is not stored.
For supervisor-call and program interruptions, a
nonzero instruction-length code identifies in half
words the length of the instruction that was last ex
ecuted. Whenever an instruction is executed by
means of EXECUTE, instruction-length code 2 is
set to indicate the length of EXECUTE and not that
of the subject instruction.
The value of a nonzero instruction-length code is
related to the leftmost two bits of the instruction.
The value is not contingent on whether the operation
code is assigned or on whether the instruction is
installed. The following table summarizes the mean
ing of the instruction-length code:
Instruction-length code
tion, indicates that the location of the instruction
causing the interruption is not made available to the
program. Instruction-length code
the following cases:
1. When a specification exception is recognized
that is due to a
one due to an odd instruction address, and the
invalid
replaced by the new
mat error cannot be attributed to an instruc
tion.
2.
(excluding those detected during implicit refer
ences to dynamic-address-translation-table
entries) or a protection exception is recognized
during a store-type reference. In these cases
the interruption due to the exception is de
layed, the length of time or number of instruc
tions of the delay being unpredictable. Neither
the location of the instruction causing the ex
ception nor the length of the last-executed in
struction is made available to the program.
When the new
Interruptions 71
