that is, when an instruction is executed with bit 5 of
the EC-·mode PSW one or when LOAD REAL AD­
DRESS is executed. Causes 1-3 are recognized on
any translation attempt; causes 4 and 5 are recog­
nized only for table entries that are actually used.
The unit of operation is suppressed.
When the exception occurs during a reference to
an operand location, the instruction-length code OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, indicating the number of halfword loca­
tions by which the instruction address has been up­
dated. It is unpredictable whether the code is 1, 2, or
3.
Programming Note
When a translation-specification exception is recog­
nized in the process of translating an instruction
address, the operation is suppressed. In this ease, the
instruction-length code OLC) is needed to derive the
address of the instruction, as the instruction address
in the old PSW has been incremented by the amount
specified by the ILC. In the case of segment·· translation and page-translation exceptions, the op­
eration is nullified, the instruction address in the old
PSW identifies the instruction, and the ILC is redun­
dant. Special-Operation Exception
A special-operation exception is recognized when a
SET SYSTEM MASK instruction is encountered in
the supervisor state and the SSM-control bit, bit 1 of
control register 0, is one.
The execution of SET SYSTEM MASK is sup­
pressed.
The instruction-length code is 2.
Monitor Event
A monitor event is recognized when MONITOR CALL is: executed and the mask bit in control regis­
ter 8 corresponding to the class specified by instruc­
tion bits 12-15 is one.
The operation is completed.
As part of the interruption, information identify­
ing the event is placed in main storage at locations
148-149 and 156-159. See "Monitoring" in the
chapter "System Control" for a detailed description
of the inlterruption condition.
The instruction-length code IS 2.
Program Event
A program event is recognized when program-event
recording is specified by the contents of control reg­
isters 9-11 and one or more of these events occur. 80 System/370 Principles of Operation
In the EC mode, the interruption may be disal­
lowed by PSW bit 1. In the BC mode, program­
event recording is disabled.
The unit of operation is completed, unless another
concurrently indicated condition has caused the unit
of operation to be nullified, suppressed, or terminat­
ed.
As part of the interruption, information identify­
ing the event is placed in main storage at locations
150-155. See "Program-Event Recording" in the
chapter "System Control" for a detailed description
of the interruption condition.
The instruction-length code is 0, 1,2, or 3. Code
o can be set only because of a protection addressing
or specification condition that is concurrently indi­
cated.
Recognition of Access Exceptions
The protection, addressing, segment-translation,
page-translation, and translation-specification excep­
tions are collectively referred to as access excep­
tions. The table "Handling of Access Exceptions"
summarizes the conditions that can cause these ex­
ceptions and the action taken when they are encoun­
tered.
An access exception due to fetching an instruction
is indicated when an instruction halfword cannot be
fetched without encountering the exception. The
exception is indicated as part of the execution of the
instruction.
Except for the specific cases described below, an
access exception due to a reference to an operand
location is indicated whenever a reference to a part
of the designated storage operand causes the excep­
tion. The exception for a partially inaccessible oper­
and is recognized even if the operation could be
completed without the use of the inaccessible part of
the operand. The access exception is indicated as
part of the execution of the instruction making the
reference.
Whenever an access to an operand location can
cause an access exception to be recognized, the word "access" is included in the list of program exceptions
in the description of the instruction. This entry also
indicates which operand can cause the exception to
be recognized and whether the exception is recog­
nized on a fetch or store access to that operand loca­
tion. Additionally, each instruction can cause an
access exception to be recognized due to instruction
fetch.
The following are exceptions or special cases
where the instruction does not explicitly specify the
extent of the storage operand or where the instruc­
tion provides for completion of execution without
the use of the entire operand. The handling of these
Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498 Implicit Explicit Translation
Translation (Operand of LRA) Indication Condition Control register contents
1 Invalid page size (CR 0 bits 8 and 9) One in bit position 10 of control register 0 segment size (CRO bits 11 and 12) Segment table entry Segment table length violation
Entry protected against fetching or storing Invalid address of entry I bit on One in an unassigned bit position
2
Page table entry
Page table length violation
Entry protected for fetching or storing Invalid address of entry I bit on One in an unassigned bit position
2
Access for instruction or data
Location protected Invalid address
Explanation: TS Translation-specification exception. Instruction TS TS TS ST A ST TS PT
A
PT TS P
A
* Operand Action Indication Action
suppress TS suppress
suppress TS suppress
** suppress TS suppress ST nullify cc3 complete
A suppress A suppress ST nullify cc1 complete TS suppress TS suppress
PT nullify cc3 complete
A suppress A suppress
PT nullify cc2 complete TS suppress TS suppress
P *
A *
Action depends on the type of reference. ST Segment-translation exception.
PT Page-translation exception.
The condition cannot occur because it is recognized as part of the
translation of the instruction address.
A Addressing exception.
P Protection exception.
cc1 Condition code 1 set.
cc2 Condition code 2 set.
2
cc3 Condition code 3 set.
The condition does not apply. Handling of Access Exceptions
cases is summarized in the table "Recognition of
Access Exceptions. " 1. When the instructions COMPARE LOGICAL (CLC or CL), COMPARE LOGICAL CHARACTERS UNDER MASK (CLM) with
a nonzero mask, and COMPARE LOGICAL LONG (CLCL) designate part of an operand
in an inaccessible location but the operation
can be completed by using the accessible oper­
:and parts, it is unpredictable whether the ac­
cess exception for the inaccessible part is indi­
cated.
2. Access exceptions are not indicated for that
part of the first operand (argument) of
TRANSLATE AND TEST (TRT) which is not
used for the completion of the operation.
3. Access exceptions are not indicated for that
part of the second operand (list) of TRANS-
A translation-specification exception for an invalid code in control register 0 bit positions 8-12 is recognized as part of the execution of
the instruction using address translation.
A translation-specification exception for a format error in a table entry
is recognized only when the execution of an instruction requires the
entry for the translation of an address.
LATE (TR) and TRANSLATE AND TEST
(TRT) which is not used for the completion of
the operation.
4. Access exceptions are not indicated for that
part of the second operand (source) of EDIT
(ED) and EDIT AND MARK (EDMK) which
is not used for the completion of the operation.
5. When the instructions MOYE WITH OFFSET (MYO), PACK (PACK), and UNPACK (UNPK) designate part of the second operand
in an inaccessible location but the operation
can be completed by using the accessible oper­
and parts, it is unpredictable whether the ex­
ception for the inaccessible part is indicated. Access exceptions are not indicated for that
part of the second operand (source) of MOYE LONG (MYCL) which is not used for the
completion of the operation.
Interruptions 81
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