I introduced by SET SYSTEM MASK or STORE THEN OR SYSTEM the ILC is 2. See "Program Status Word" in the chapter "System Control" for a discussion of when the ex­
ceptions associated with the PSW are recognized.
Data Exception
A data exception is recognized when:
1. The sign or digit codes of operands in the
decimal-feature instructions or in CONVERT TO BIN AR Yare invalid.
2. The! operand fields in ADD DECIMAL, COM­ PARE DECIMAL, DIVIDE DECIMAL, MULTIPLY DECIMAL, and SUBTRACT DECIMAL overlap in a way other than with
coincident rightmost or operand fields in ZERO AND ADD overlap, and the rightmost byte of the second operand is to the right of
the rightmost byte of the first operand.
3. The multiplicand in MULTIPLY DECIMAL
has an insufficient number of high-order zeros.
Except for EDIT and EDIT AND MARK, the
operation is suppressed when a sign code is invalid,
regardless of whether any other condition causing
the exception exists; otherwise, the operation is ter­
minated. However, the contents of the sign position
in the rightmost byte of the result field either remain
unchanged or are set to the preferred sign the
contents of the remainder of the result field are un­
predictable.
[n the case of EDIT and EDIT AND MARK, an
invalid sign code is not recognized, and the opera­
tion is terminated on a data exception.
The instruction-length code is 2 or 3.
Programming Note
When, on a program interruption for data exception,
the program finds that a sign code is invalid, the
operation has been suppressed if the following two
conditions are met: • The invalid sign is not located in the numerical
portion of the result field . • The sign code appears in a position specified by
the instruction to be checked for valid sign.
(This condition excludes the first operand of ZERO AND ADD and both operands of EDIT
and EDIT AND MARK.)
An invalid sign code for the rightmost byte of the
result field is not generated when the operation is
terminated. However, an invalid second-operand
sign code is not necessarily preserved when it ap­
pears in the numerical portion of the result field.
78 System/370 Principles of Operation
Fixed-Point-Overflow Exception
A fixed-point-overflow exception is recognized
when a carry occurs out of the high-order bit posi­
tion in fixed-point arithmetic operations, or high­
order significant bits are lost during the algebraic
left-shift operations.
The interruption may be disallowed in the BC
mode by PSW bit 36, and in the EC mode by PSW bit 20. The operation is completed by setting condition
code 3 but otherwise ignoring the information placed
outside the register.
The instruction-length code is 1 or 2.
Fixed-Point-Divide Exception
A fixed-point-divide exception is recognized when in
fixed-point division the divisor is zero or the quo­
tient exceeds the register size, or when the result of CONVERT TO BINARY exceeds 31 bits.
In the case of division, the operation is sup­
pressed. Execution of CONVERT TO BINARY is
completed by ignoring the high-order bits that can­
not be placed in the register.
The instruction-length code is 1 or 2.
Decimal-Overflow Exception
A decimal-overflow exception is recognized when
one or more significant high-order digits are lost
because the destination field in a decimal operation
is too small to contain the result.
The interruption may be disallowed in the BC
mode by PSW bit 37, and in the EC mode by PSW bit 21.
The operation is completed by setting condition
code 3 but otherwise ignoring the overflow informa­
tion.
The instruction-length code is 2 or 3.
Decimal-Divide Exception
A decimal-divide exception is recognized when in
decimal division the divisor is zero or the quotient
exceeds the specified data field size.
The operation is suppressed .
The instruction-length code is 2 or 3.
Exponent-Overflow Exception
An exponent-overflow exception is recognized when
the result characteristic in floating-point addition,
subtraction, multiplication, or division exceeds 127
and the result fraction is not zero.
The operation is completed. The fraction is nor­
malized, and the sign and fraction of the result re­
main correct. The result characteristic is made 128
smaller than the correct characteristic.
The instruction-length code is 1 or 2.

Exponent-Underflow Exception
An exponent-underflow exception is recognized
when the result characteristic in floating-point addi­
tion, subtraction, multiplication, halving, or division
is less than zero and the result fraction is not zero.
The interruption may be disallowed in the BC
mode by PSW bit 38, and in the EC mode by PSW bit 22.
The operation is completed. The setting of the
exponent-underflow mask also affects the result of
the operation. When the mask bit is zero, the sign,
characteristic, and fraction are set to zero, making
the result a true zero. When the mask bit is one, the
fraction is normalized, the characteristic is made 128
larger than the correct characteristic, and the sign
and fraction remain correct.
The instruction-length code is 1 or 2.
Significance Exception
A significance exception is recognized when the
result fraction in floating-point addition or subtrac­
tion is zero.
The interruption may be disallowed in the BC
mode by PSW bit 39, and in the EC mode by PSW bit 23.
The operation is completed. The significance
mask affects also the result of the operation. When
the mask bit is zero, the operation is completed by
replacing the result with a true zero. When the mask
bit is one, the operation is completed without further
change to the characteristic and sign of the result.
The instruction-length code is 1 or 2.
Floating-Point-Divide Exception
A floating-point-divide exception is recognized when
a floating-point division by a number with a zero
fraction is attempted.
The operation is suppressed.
The instruction-length code is 1 or 2.
Segment-Translation Exception
A exception is recognized when:
1. The segment-table entry is outside the segment
table.
2. The segment-invalid bit has the value 1.
The exception is recognized as part of the execu­
tion of the instruction that needs the segment-table
entry in the translation of either the instruction or
operand address, except for the operand address in LOAD REAL ADDRESS, in which case the condi­
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad­
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca-
tion 144. When 2,048-byte pages are used, the low­
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Page-Translation Exception
A page-translation exception is recognized when:
1. The page-table entry is outside the page table.
2. The page-invalid bit has the value 1.
The exception is recognized as part of the execu­
tion of the instruction that needs the page-table en­
try in the translation of either the instruction or oper­
and address, except for the operand address in LOAD REAL ADDRESS, in which case the condi­
tion is indicated by the setting of the condition code.
The unit of operation is nullified.
The segment and page portion of the logical ad­
dress causing the exception is placed in main storage
at locations 145-147, and zeros are placed at loca­
tion 144. When 2,048-byte pages are used, the low­
order 11 bits of the address are unpredictable; when
4,096-byte pages are used, the low-order 12 bits of
the address are unpredictable.
When the exception occurs during a reference to
an operand location, the instruction-length code
OLC) is 1, 2, or 3 and indicates the length of the
instruction causing the exception. When the excep­
tion occurs during fetching of an instruction, the ILC
is 1, 2, or 3, the indication being unpredictable.
Translation-Specification Exception
A translation-specification exception is recognized
when:
1. Bit positions 8 and 9 of control register 0 con-­ tain values 00 or 11.
2. Bit position 10 of control register 0 contains a
one.
3. Bit positions 11 and 12 of control register 0 contain values 01 or 11.
4.
Bit positions 4-7 or 29-30 in a valid segment­
table entry do not contain zeros (on some
models these bit positions are not checked for
zeros).
5. Depending on the page size, the one or two bit
positions next to the low-order bit in a valid
page-table entry do not contain zeros.
The exception is recognized only as part of the
execution of an instruction using address translation,
Interruptions 79