Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
Conversely, the request is not cleared by the inter­
ruption, and, if the condition persists, more than one
interruption may result from a single occurrence of
the condition. The condition is indicated by an external­
interruption code of 1004 (hex). In the Ee mode,
zeros are stored at locations 132-133. The submask bit is located in bit position 20 of
control register O. This bit is initialized to zero. CPU Timer
An interruption request for the CPU timer exists whenever the CPU timer value is negative (bit 0 of
the CPU timer is one). If the value is made positive
before the request is honored, the request does not
remain pending, and no interruption occurs. Con­
versely, the request is not cleared by the interrup­
tion, and, if the condition persists, more than one
interruption may occur from a single occurrence of
the condition.
The condition is indicated by an external­
interruption code of 1005 (hex). In the EC mode,
zeros are stored at locations 132-133.
The submask bit is located in bit position 21 of
control register O. This bit is initialized to zero.
Input/Output Interruption
The input/output (I/O) interruption provides a
means by which the CPU responds to conditions in I/O devices and channels.
An I/O interruption causes the old PSW to be
stored at location 56, a channel status word to be
stored at location 64, and a new PSW to be fetched
from location 120. Upon detection of equipment
errors, additional information may be stored in the
form of a limited channel logout at location 176 and
in the form of an I/O extended logout starting at the
location designated by the contents of locations 173-
175.
When the old PSW specifies the BC mode, the
interruption code in PSW bit positions 16-31 identi­
fies the channel and device causing the interruption:
the channel address appears in the high-order eight
bit positions and the device address in the low-order
eight. The·instruction-Iength code is unpredictable.
When the old PSW specifies the EC mode, the de­
vice address is placed at location 187, the channel addre:ss at location 186, and zeros are stored at loca­
tion 185. An I/O interruption can occur only while the CPU is enabled for interruption by the channel pre­
senting the request. Whether the CPU is enabled for
interruption by a channel is controlled by mask bits
88 System/370 Principles of Operation
in the PSW and by channel masks in control register
2, and the method of control depends on whether
the current PSW specifies the BC or EC mode.
Channel mask bits are located in control register
2 starting at bit position 0 and extending for as many
contiguous bit positions as the number of channels
provided. The assignment is such that a bit is as­
signed to the channel whose address is equal to the
position of the bit in control register 2. Channel­
mask bits for installed channels are initialized to one.
The state of channel mask bits for unavailable chan­
nels is unpredictable.
When the current PSW specifies the BC mode,
interruptions from channels 6 and up are controlled
by the I/O mask bit, PSW bit 6, in conjunction with
the corresponding channel mask bit: the channel can
cause an interruption only when the I/O mask is one
and the corresponding channel mask is one. Interrup­
tions from channels 0-5 are controlled by channel
masks 0-5 in the PSW; an interruption can occur
only when the mask corresponding to the channel is
one. In the BC mode, bits 0-5 in control register 2
do not participate in controlling I/O interruptions;
they are, however, preserved in the control register.
When the current PSW specifies the EC mode,
each channel is controlled by the I/O mask bit and
the corresponding channel mask bit in control regis­
ter 2: the channel can cause an interruption only
when the I/O mask bit ts one and the corresponding
channel mask bit is one.
When the CPU becomes enabled for a pending
I/O-interruption condition, the interruption occurs
at the completion of the instruction execution or
interruption that causes the enabling.
A request for an I/O interruption may occur at
any time, and more than one request may occur at
the same time. The requests are preserved and re­
main pending in channels or devices until accepted
by the CPU. Priority is established among requests
so that only one interruption request is processed at
a time. For more details
1 see the section "Input/Output Interruptions" in the chapter on I/O operations.
Restart
The restart interruption PFovides a means for the
operator or another CPU to invoke the execution of
a program. The CPU cannot be disabled for this
interruption.
A restart interruption causes the old PSW to be
stored at main-storage location 8 and a new PSW to
be fetched from location O. In the BC mode, the
instruction-length code in the PSW is unpredictable,

and zeros are stored in the interruption-code field.
In the EC mode, the instruction-length and interrup­
tion codes are not stored.
If the CPU is in the operating state, the exchange
of the PSW s occurs at the completion of the current
unit of operation and after all pending interruption
conditions for which the CPU is enabled have been
taken. In this case, it depends on the model if the CPU temporarily enters the stopped state as part of
the execution of the restart operation. If the CPU is
in the stopped state, the CPU enters the operating
state and exchanges the PSW s without first taking
any pending interruptions.
The restart interruption is initiated by activating
the restart key on the system console. In a multipro­
cessing system, the operation can also be initiated at
the addressed CPU by issuing SIGNAL PRO,­ CESSOR, specifying the restart order.
Programming Note
In order to perform restart when the CPU is in the
check-stop state, the CPU has to be reset. This can
be accomplished by means of program reset, which
does not clear the contents of program-addressable
registers, including the control registers, but causes
the attached channels to be reset.
Priority of Interruptions
During the execution of an instruction, several
interruption-causing events may occur simultaneous­
ly. The instruction may give rise to a program inter­
ruption, a request for an external interruption may
be received, equipment malfunctioning may be de­
tected, an I/O-interruption request may be made,
and the restart key may be activated. Instead of the
program interruption, a supervisor-call interruption
might occur; or both can occur if the program-event­
recording facility is installed. Simultaneous interrup­
tion requests are honored in a predetermined order.
An exigent machine-check condition has the high­
est priority. When it occurs, the current operation is
terminated or nullified. Program and supervisor-call
interruptions that would have occurred as a result of
the current operation may be eliminated. Any pend­
ing repressible machine-check conditions may be
indicated with the exigent machine-check interrup­
tion. Every reasonable attempt is made to limit the
side effects of an exigent machine-check condition,
and, normally, requests for I/O and external inter­
ruptions remain unaffected.
In the absence of an exigent machine-check con­
dition, requests for interruption existing concurrently
at the end of a unit of operation are honored in the Page ofGA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
following order of priority (the conditions are listed
in descending order of priorities):
Supervisor call
Program
Repressible machine-check
External
Input/ output
Restart
The processing of multiple simultaneous interrup­
tion requests consists in storing the old PSW and
fetching the new PSW belonging to the interruption
first taken. This new PSW is subsequently stored
without the execution of any instructions, and the
new PSW associated with the next interruption is
fetched. This storing and fetching continues until no
more interruptions are to be serviced. The priority is
reevaluated after the new PSW is loaded. Each eval­
uation is performed taking into consideration any ad­
ditional interruptions which may have become pend­
ing. Additionally, external and I/O interruptions, as
well as· machine-check interruptions due to repres-
sible conditions, are taken only if the current PSW at
the instant of evaluation indicates that the CPU is inter­
ruptible for the cause.
Instruction execution is resumed using the last­
fetched PSW. The order of executing interruption
subroutines is therefore the reverse of the order in
which the PSWs are fetched.
If the new PSW for a program interruption has an
unacceptable instruction address (the instruction
address is odd or causes an access exception to be
recognized), another program interruption occurs.
Since this second interruption introduces the same
unacceptable PSW, a string of interruptions is estab­
lished. These program exceptions are recognized as
part of the execution of the following instruction,
and the string may be broken by an I/O, external, or
restart interruption or the stop function.
If the new PSW for a program interruption con­
tains a one in an unassigned bit position in an EC­
mode PSW, or if it specifies the EC mode in a CPU that does not have the EC facility installed, or if it
specifies any other facility that is not installed on the
CPU, another program interruption occurs. This
condition is of higher priority than restart, I/O, ex­
ternal, or repressible machine-check conditions, or
the stop function, and CPU reset has to be used to
break the loop.
Interruption loops of other interruption classes
can also exist if the new PSW is enabled for the
same interruption. These include machine-check
interruptions and external interruptions due to
channel-available or PCI conditions. Interruption
loops involving more than one interruption class can
Interruptions 89