Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
also exist. For example, assume that the CPU timer
is negative and the CPU-timer subclass mask is one.
If the external new PSW has an exception which is
recognized as part of early recognition, and the pro­
gram new PSW is enabled for external interruptions,
then a series of interruptions occur, alternating be­
tween external and program. Even more complex
loops are possible. So long as more interruptions
must be serviced, the loop cannot be broken by em­
ploying the stop function; CPU reset is required. Similarly, CPU reset has to be invoked to termi­
nate the condition that exists when an interruption is
attempted with a prefix value designating a main­
storage location that is not available to the CPU. On some models, when an excessive number of consecutive interruptions is detected which cannot
be broken by means of the stop function, the CPU enters a special state that can be exited only by use
of CI)U reset.
Interruptions for all requests for which the CPU is
enabled are taken before the CPU is placed in the
stopped state. When the CPU is in the stopped state,
restart has a higher priority than pending I/O, exter­
nal, or repressible machine-check conditions. Progl'amming Note
The order in which concurrent interruption requests
are honored can be changed to some extent by
masking.
Assigned Main-Storage Locations Real' Main Storage
The chart "Assigned Locations in Real Main Stor­ age" shows the format and extent of the assigned
locations in real main storage. In a multiprocessing
system, real storage addresses are transformed to
absolute addresses by means of prefixing. The loca­
tions are used as follows. Unless specifically noted,
the usage applies to both the BC and EC modes. 0- 7 Restart New P S W: The new PSW is
fetched from locations 0-7 during the re.­
start interruption.
8-15 Restart Old PSW: The current PSW is
stored as the old PSW at locations 8-15
during the restart interruption. 24-63 64-71 Interruption Old PSWs: The current PSW is stored as the old PSW at locations
24-31, 32-39, 40-47, 48-55, and 56-63
during the external, supervisor-call, pro­
gram, machine-check, and input/output
interruptions, respectively. CSW: The channel status word (CSW) is
stored at locations 64-71 during an I/O 90 System/370 Principles of Operation
interruption. It, or portions thereof, may
be stored during the execution of START I/O, START I/O FAST RELEASE, TEST I/O, CLEAR I/O, HALT I/O, or
HALT DEVICE, in which case condition
code 1 is set.
72-75 CA W: The channel address word (CAW)
is fetched from locations 72-75 during
the execution of START I/O and START I/O FAST RELEASE. 80-83 Interval Timer: Locations 80-83 contain
the interval timer. The timer is updated
whenever the CPU is in the operating
state. Depending on the resolution of the
timer, the low-order locations may not be
updated.
88-127 Interruption New PSWs: The new PSW is fetched from locations 88-95, 96-103,
104-111, 112-119, and 120-127 during
the external, supervisor-call, program,
machine-check, and input/ output inter­
ruptions, respectively.
132-133 Processor Address: During an external
interruption due to malfunction alert,
emergency signal, or external call, the
processor address associated with the
source of the interruption is stored at lo­
cations 132-133. For all other external
interruption conditions, zeros are stored
at locations 132-133 when the old PSW specified EC mode, and the field remains
unchanged when the old PSW specified
the BC mode.
134-135 External-Interruption Code: During an
external interruption in the EC mode, the
interruption code is stored at locations
134-135.
136-139 Supervisor-Call-Interruption
Identification: During a supervisor-call
interruption in the EC mode, the
instruction-length code is stored in bit
positions 5 and 6 of location 137, and the
interruption code is stored at locations
138-139. Zeros are stored at location 136
and in the remaining bit positions of 137.
140-143 Program-Interruption Identification: Dur­
ing a program interruption in the EC
mode, the instruction-length code is
stored in bit positions 5 and 6 of location
141, and the interruption code is stored
at locations 142-143. Zeros are stored at
location 140 and in the remaining bit
positions of 141.

144-147 Translation-Exception Address: During a
program interruption due to a segment­
translation exception or a page­
translation exception, the translation­
exception address is stored at locations
145-147, and zeros are stored at location
144. This field can be stored only when
the old program PSW specifies the EC
mode.
148-149 Monitor Class Number: During a pro­
gram interruption due to a monitor event,
the monitor class number is stored at lo­
cation 149, and zeros are stored at 148.
This field can be stored in either the BC
orEC modes. PER Code: During a program interrup­
tion due to a program event, the
program-event-recording (PER) code is
stored in bit positions 0-3 of location 150, and zeros are stored in bit positions
4-7 and at location 151. This field can
be stored only when the instruction caus­
ing the PER condition was executed un­
der the control of a PSW specifying the
EC mode.
152-155 PER Address: During a program interrup­
tion due to a program event, the
program-event-recording (PER) address
is stored at locations 153-155, and zeros
are stored at location 152. This field can
be stored only when the instruction caus­
ing the PER condition was executed un­
der the control of a PSW specifying the
EC mode.
156-159 Monitor Code: During a program inter­
ruption due to a monitor event, the moni­
tor code is stored at locations 157-159,
and zeros are stored at location 156.
This field can be stored in either the BC
orEC mode.
168-171 Channel ID: The four-byte channel­
identification information is stored at lo­
cations 168-171 during the execution of STORE CHANNEL 10. 172-175 IOEL Address: The I/O-extended­
logout address is fetched from locations
172-175 during the I/O-extended-logout
operation.
176-179 Limited Channel Logout: The limited­
channel-logout information is stored at
locations 176-179. This field may be
Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498
stored only when the CSW or a portion
of the CSW is stored. It may be stored in
either the BC or EC mode.
185-187 I/O Address: During an I/O interruption
in the EC mode, the two-byte I/O ad­
dress is stored at locations 186-187, and
zeros are stored at location 185.
216-511 Machine-Check Interruption Code, Save
Area, and Logout: Information may be
stored at locations 216-239 and 248-511
during a machine-check interruption, and
information may be stored at locations
256-351 during an I/O interruption. Ad­
ditionally, the contents of locations 256-
351 may be changed at any time, subject
to the asynchronous-fixed-logout-control
bit in control register 14.
Absolute Main Storage
The chart "Assigned Locations in Absolute Main Storage" shows the format and extent of the as­
signed locations in absolute main storage. The loca­
tions are as follows, and the usage applies to both
the BC and EC modes. 0-7 IPL PSW: The first eight bytes read
during the IPL initial read operation are
stored at locations 0-7. The contents of
these locations are used as the new PSW at the completion of the IPL operation.
These locations may also be used for
temporary storage at the initiation of the
IPL operation.
8-15 IPL CCW1: Bytes 8-15 read during the
IPL initial read operation are stored at
locations 8-15. The contents of these lo­
cations are ordinarily used as the second
CCW in an IPL CCW chain after com­
pletion of the IPL initial read operation.
16-23 IPL CCW2: Bytes 16-23 read during the
IPL initial read operation are stored at
locations 16-23. The contents of these
locations may be used as the third CCW
of an IPL CCW chain after completion of
the IPL initial read operation.
216-511 Store-Status Save Area: Information is
stored at locations 216-231,256-271,
and 352-511 during the execution of the
store-status operation.
Interruptions 91