supervisor-program PSW key to its original value.
Caution must be observed, however, in handling any
resulting protection exceptions since such exceptions
may cause the operation to be terminated and, on
some models, the resulting interruption may be de­
layed and indicated with an instruction-length code
of zero.
Set Storage Key SSK [RR]
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the register designated
by the R2 field is replaced by the contents of the
register designated by the Rl field.
Bits 8-20 of the register designated by the R2
field designate a block of 2,048 bytes in real main
storage. Bits 0-7 and 21-27 of the registerarc ig­
nored. Bits 28-31 of the register must be zeros; oth­
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans­
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The seven-bit key is obtained from bit positions 24-30 of the register designated by the Rl field. The
contents of bit positions 0-23 and 31 of the register
are ignored. When dynamic address translation is not
installed, bits 29 and 30 are ignored.
Condition Code: The code remains unchanged.
Program Exceptiom:
Privileged operation
Access (addressing for operand access only, oper­
and 2)
Specification
110 Systern/370 Principles of Operation Set System Mask SSM [S] 80 o 8 16 20 31
Bits 0-7 of the current PSW are replaced by the byte
at the location designated by the second-operand
address.
When the SSM-suppression facility is installed,
the execution of the instruction is subject to the
SSM-suppression bit, bit 1 of control register O. When the bit is zero, the instruction is executed nor­
mally. When the bit is one and the CPU is in the
supervisor state, a special-operation exception is
recognized, and the operation is suppressed.
The operation is suppressed on protection and
addressing exceptions.
The value to be loaded into the PSW is not
checked for validity before loading. However, im­
mediately after loading, a specification exception is
recognized, and a program interruption occurs, if the CPU is in the EC mode and the contents of bit posi­
tions 0 and 2-4 of the PSW are not all zeros. In this
case, the instruction is completed, and the
instruction-length code is set to 2.
Bits 8-15 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Special operation
Signal Processor SIGP AE
o 8 12 16 [RS] 20 31
An eight-bit order code is transmitted to the CPU designated by the processor address contained in the
third operand. The result is indicated by the condi­
tion code and may be detailed by status assembled in
the first-operand location.
The second-operand address is not used to ad­
dress data; instead, bits 24-31 of the address contain
the eight-bit order code. Bits 8-23 of the second­
operand address are ignored. The order code speci­
fies the function to be performed by the addressed
CPU. The assignment and definition of order codes
appears in the chapter "Multiprocessing." The 16-bit binary number contained in bit posi­
tions 16-31 of the general register designated by the
R3 field forms the processor address. The high-order
16 bits of the register are ignored.
A serialization function is performed. CPU oper­
ation is delayed until all previous accesses by this CPU to main storage have been completed, as ob­
served by channels and other CPUs, and then the
signaling occurs. No subsequent instructions or their
operands are accessed by this CPU until the execu­
tion of the instruction is completed.
When the order code is accepted and no nonzero
status is returned, condition code 0 is set. When
status information is generated by this CPU or re­
turned by the addressed CPU, the status is placed in
the general register designated by the Rl field, and
condition code 1 is set.
When the access path to the addressed CPU is
busy or the addressed CPU is operational and in a
state where it cannot respond to the order code,
condition code 2 is set.
When the addressed CPU is not operational (that
is, it is not provided, or it is not configured to this
CPU, or it is in certain customer-engineer test modes,
or its power is off), condition code 3 is set.
A more detailed discussion of the condition-code
settings for SIGNAL PROCESSOR is contained in
the chapter "Multiprocessing." Resulting Condition Code:
o Order code accepted
1 Status stored
2 Busy
3 Not operational Program Exceptions:
Operation (if the multiprocessing feature is not
installed)
Privileged operation
Programming Notes
The execution time on the issuing CPU for SIG­ NAL PROCESSOR may vary depending on the
model, the order code, and the state of the addressed
CPU. In some cases, the execution time may be sev­
eral seconds.
To ensure that presently written programs will be
executed properly when new facilities using addi­
tional bits are installed, only zeros should appear in
the unused bit positions of the second-operand ad­
dress and in bit positions 0-15 of the register desig-
nated by the R3 field. Store Clock Comparator 8207 o 16 20 31
The current value of the clock comparator is stored
at the doubleword designated by the second-operand
address.
Zeros are provided for the rightmost bit positions
that are not used for comparison with the time-of­
day clock.
The operand must be designated on a doubleword
boundary; otherwise, a specification exception is
recognized, and the operation is suppressed. The
operation is suppressed on protection and addressing
exceptions.
Condition Code: The code remains unchanged. Program Exceptions:
Operation (if the clock comparator is not in-
stalled)
Privileged operation
Access (store, operand 2)
Specification Store Control
STCTL Rl,R3,D2(B2) I B6
o 8 12 16 [RS] 20 31
The set of control registers starting with the control
register designated by the Rl field and ending with
the control register designated by the R3 field is
stored at the locations designated by the second­
operand address.
The storage area where the contents of the con­
trol registers are placed starts at the location desig­
nated by the second-operand address and continues
through as many storage words as the number of
control registers specified. The contents of the con­
trol registers are stored in ascending order of their
addresses, starting with the control register designat­
ed by the Rl field and continuing up to and includ­
ing the control register designated by the R3 field,
with control register 0 following control register 15.
The contents of the control registers remain un­
changed.
System-Control Instructions 111
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