supervisor-program PSW key to its original value.
Caution must be observed, however, in handling any
resulting protection exceptions since such exceptions
may cause the operation to be terminated and, on
some models, the resulting interruption may be de
layed and indicated with an instruction-length code
of zero.
Set Storage KeySSK [RR]
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the register designated
by the R2 field is replaced by the contents of the
register designated by the Rl field.
Bits8-20 of the register designated by the R2
field designate a block of2,048 bytes in real main
storage. Bits0-7 and 21-27 of the registerarc ig
nored. Bits 28-31 of the register must be zeros; oth
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The seven-bit key is obtained from bit positions24-30 of the register designated by the Rl field. The
contents of bit positions0-23 and 31 of the register
are ignored. When dynamic address translation is not
installed, bits 29 and30 are ignored.
Condition Code: The code remains unchanged.
Program Exceptiom:
Privileged operation
Access (addressing for operand access only, oper
and 2)
Specification
110Systern/370 Principles of Operation Set System Mask SSM [S] 80 o 8 16 20 31
Bits0-7 of the current PSW are replaced by the byte
at the location designated by the second-operand
address.
When the SSM-suppression facility is installed,
the execution of the instruction is subject to the
SSM-suppression bit, bit 1 of control registerO. When the bit is zero, the instruction is executed nor
mally. When the bit is one and theCPU is in the
supervisor state, a special-operation exception is
recognized, and the operation is suppressed.
The operation is suppressed on protection and
addressing exceptions.
The value to be loaded into thePSW is not
checked for validity before loading. However, im
mediately after loading, a specification exception is
recognized, and a program interruption occurs, if theCPU is in the EC mode and the contents of bit posi
tions0 and 2-4 of the PSW are not all zeros. In this
case, the instruction is completed, and the
instruction-length code is set to 2.
Bits 8-15 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Special operation
Signal ProcessorSIGP AE
o 8 12 16[RS] 20 31
An eight-bit order code is transmitted to theCPU designated by the processor address contained in the
third operand. The result is indicated by the condi
tion code and may be detailed by status assembled in
the first-operand location.
The second-operand address is not used to ad
dress data; instead, bits 24-31 of the address contain
the eight-bit order code. Bits 8-23 of the second
operand address are ignored. The order code speci
fies the function to be performed by the addressed
Caution must be observed, however, in handling any
resulting protection exceptions since such exceptions
may cause the operation to be terminated and, on
some models, the resulting interruption may be de
layed and indicated with an instruction-length code
of zero.
Set Storage Key
o 8 12 15
The key in storage associated with the block that is
addressed by the contents of the register designated
by the R2 field is replaced by the contents of the
register designated by the Rl field.
Bits
field designate a block of
storage. Bits
nored. Bits 28-31 of the register must be zeros; oth
erwise, a specification exception is recognized, and
the operation is suppressed.
The address designating the storage block, being a
real address, is not subject to dynamic address trans
lation. Hence, the reference to the key cannot cause
segment-translation, page-translation, and
translation-specification exceptions to be recognized,
and an addressing exception can be caused only by
an invalid storage-block address (as contrasted to an
invalid address of a table entry). The reference to
the key is not subject to a protection exception.
The seven-bit key is obtained from bit positions
contents of bit positions
are ignored. When dynamic address translation is not
installed, bits 29 and
Condition Code: The code remains unchanged.
Program Exceptiom:
Privileged operation
Access (addressing for operand access only, oper
and 2)
Specification
110
Bits
at the location designated by the second-operand
address.
When the SSM-suppression facility is installed,
the execution of the instruction is subject to the
SSM-suppression bit, bit 1 of control register
mally. When the bit is one and the
supervisor state, a special-operation exception is
recognized, and the operation is suppressed.
The operation is suppressed on protection and
addressing exceptions.
The value to be loaded into the
checked for validity before loading. However, im
mediately after loading, a specification exception is
recognized, and a program interruption occurs, if the
tions
case, the instruction is completed, and the
instruction-length code is set to 2.
Bits 8-15 of the instruction are ignored.
Condition Code: The code remains unchanged.
Program Exceptions:
Privileged operation
Access (fetch, operand 2)
Specification
Special operation
Signal Processor
o 8 12 16
An eight-bit order code is transmitted to the
third operand. The result is indicated by the condi
tion code and may be detailed by status assembled in
the first-operand location.
The second-operand address is not used to ad
dress data; instead, bits 24-31 of the address contain
the eight-bit order code. Bits 8-23 of the second
operand address are ignored. The order code speci
fies the function to be performed by the addressed