The interruption system permits the CPU to change
its stat.e as a result of conditions external to the sys­
tem, within the system, or within the CPU itself. To
permit fast response to conditions of high priority
and immediate recognition of the type of condition,
interrUlption conditions are grouped into six classes:
input-output, external, program, supervisor call, ma­
chine check, and restart.
Interruption Action
An interruption consists in storing the current PSW as an old PSW, storing further detail information
identifying the cause of the interruption, and fetch­
ing a new PSW. Processing resumes as specified by
the new PSW. The old PSW stored on an interruption normally
contailtls the address of the instruction that would
have been executed next had the interruption not
occurred, thus permitting resumption of the inter­
rupted program. For program and supervisor-call
interruptions, the information stored also contains a
code that identifies the length of the last-executed
instruction, thus permitting the program to respond
to the cause of the interruption. In the case of some
program conditions for which the execution of the
instruction causing the interruption normally is re­
sumed, the instruction address directly identifies the
instruction last executed.
Except for restart, an interruption can take place
only when the CPU is in the operating state. The
restart interruption can occur with the CPU either
stopped or operating. The details of source identification, location de­
termination, and instruction execution are explained
in later sections and are summarized in the table
"Intenruption Action." Programming Note See the section "Program Status Word" in the chap­
ter "System Control" for details as to when the new PSW introduced by an interruption is checked for
format errors. Sour,ce Identification
The six classes of interruptions (I/O, external, pro­
gram, supervisor call, machine check, and restart)
are distinguished by the storage locations at which
the old PSW is stored and from which the new PSW is fetched. For most classes, the causes are further
identified by an interruption code and, for some
classes:, by additional information placed in main
storage during the interruption. For I/O, external,
supervisor-call, and program interruptions, the inter­
ruption code comprises 16 bits and is placed in the
old PSW when the old PSW specifies the BC mode 70 System/370 Principles of Operation
and in separate main-storage locations when the EC
mode is specified.
For I/O interruptions, additional information is
provided by the contents of the channel status word (CSW) stored at location 64, and further informa­
tion may be provided by the limited channel logout
stored at location 176 and by the I/O extended log­
out.
For program interruptions, additional information
may be provided in the form of the translation­
exception address, monitor-class number and moni­
tor code, and PER code and PER address stored at
locations 144-159.
For machine-check interruptions, the interruption
code comprises 64 bits and is placed in main storage
at location 232. Additional information for identify­
ing the cause of the interruption and for recovering
the state of the CPU may be provided by the con­
tents of the logout and save areas.
The assignment and format of the permanently
allocated storage locations is shown in the table
"Permanently Assigned Storage Locations" at the
end of this chapter.
Enabling and Disabling
The CPU may be enabled or disabled for all I/O, external, and machine-check interruptions and for
some program interruptions. When the CPU is ena­
bled for a class of interruptions, these interruptions
can take place. When the CPU is disabled, the condi­
tions that cause I/O interruptions remain pending,
and the disallowed program-interruption conditions
are ignored, except that some causes are indicated
also by the setting of the condition code. External
and machine-check conditions, depending on the
type, are ignored or remain pending.
Program interruptions for which mask bits are not
provided, as well as the supervisor-call and restart
interruptions, are always taken.
Whether the CPU is enabled or disabled for a
particular type of interruption is controlled by mask
bits in the current PSW and in control registers. The
setting of the mask bits may disallow all interrup­
tions within the class or may selectively allow inter­
ruptions for particular causes. This control is pro­
vided by assigning a mask bit in the PSW to a partic­
ular cause, such as in the case of the four maskable
program interruption conditions, or by providing a
hierarchy of masks, where a mask in the PSW con­
trols all interruptions within a type, and masks in
control registers provide more detailed control over
the sources.
When the mask bit is one, the CPU is enabled for
the corresponding interruptions. When the mask bit
is zero, these interruptions are disallowed. Interrup-

tions that are controlled by a hierarchy of masks are
allowed only when all mask bits in the hierarchy are
ones.
Programming Note
Mask bits in the PSW provide a means of disabling
all maskable interruptions; thus, subsequent inter­
ruptions can be disallowed by the new PSW intro­
duced by an interruption. Furthermore, the mask
bits can be used to establish a hierarchy of interrup­
tion priorities, where a condition in one class can
interrupt the program handling a condition in anoth­
er class but not vice versa. To prevent an
interruption-handling routine from being interrupted
before the necessary housekeeping steps are per­
formed, the new PSW must disable the CPU for
further interruptions within the same class or within
a class of lower priority.
Since the mask bits in control registers are not
changed as part of the interruption procedure, these
masks cannot be used to prevent an interruption
immediately after a previous interruption in the same
class. The mask bits in control registers provide a
means for selectively enabling the CPU for some
sources and disabling it for others within the same
class.
Instruction-Length Code
The instruction-length code OLC) occupies two bit
positions and provides the length of the last instruc­
tion executed. It permits identifying the instruction
causing the interruption when the instruction address
in the old PSW designates the next sequential in­
struction. The ILC is provided also by the BRANCH
AND LINK instructions.
In an old PSW specifying the BC mode, the
instruction-length code is stored in bit positions 32
and 33. It is meaningful, however, only after a pro­
gram or supervisor-call interruption. For I/O, exter­
nal, machine-check, and restart interruptions, the
code does not indicate the length of the last­
executed instruction and is unpredictable. Similarly,
the ILC is unpredictable in the PSW stored during
execution of the store-status function and when the PSW is displayed.
When the old PSW specifies the EC mode, the
instruction-length code for supervisor-call and pro­
gram interruptions is stored in bit positions 5 and 6
of the bytes at locations 137 and 141, respectively.
For I/O, external, machine-check, and restart inter­
ruptions the code is not stored.
For supervisor-call and program interruptions, a
nonzero instruction-length code identifies in half­
words the length of the instruction that was last ex­
ecuted. Whenever an instruction is executed by
means of EXECUTE, instruction-length code 2 is
set to indicate the length of EXECUTE and not that
of the subject instruction.
The value of a nonzero instruction-length code is
related to the leftmost two bits of the instruction.
The value is not contingent on whether the operation
code is assigned or on whether the instruction is
installed. The following table summarizes the mean­
ing of the instruction-length code: ILC Decimal Binary Instruction Bits 0-1 I nstruction Length 0 00 Not available 01 00 One halfword 2 10 01 Two halfwords 2 10 10 Two halfwords 3 11 11 Three halfwords Zero ILC
Instruction-length code 0, after a program interrup­
tion, indicates that the location of the instruction
causing the interruption is not made available to the
program. Instruction-length code ° occurs only in
the following cases:
1. When a specification exception is recognized
that is due to a PSW format error, other than
one due to an odd instruction address, and the
invalid PSW has been introduced by LOAD PSW or an interruption. In the case of LOAD PSW, the address of the instruction has been
replaced by the new PSW. When the invalid PSW is introduced by an interruption, the for­
mat error cannot be attributed to an instruc­
tion.
2. On some models, when an addressing exception
(excluding those detected during implicit refer­
ences to dynamic-address-translation-table
entries) or a protection exception is recognized
during a store-type reference. In these cases
the interruption due to the exception is de­
layed, the length of time or number of instruc­
tions of the delay being unpredictable. Neither
the location of the instruction causing the ex­
ception nor the length of the last-executed in­
struction is made available to the program.
When the new PSW introduced by LOAD PSW or a supervisor-call interruption has a format error,
Interruptions 71