Page of GA22-7000-4 Revised September 1, 1975
By TNL: GN22-0498 The first operand is compared with the seeond oper­
and, and the result is indicated in the condition
code. The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The operation proceeds left to right and
ends as soon as an inequality is found or an end of
the fields is reached.
When part of an operand in CL or CLC is desig­
nated in an inaccessible location but the operation
can be completed by using the accessible operand
parts, it is unpredictable whether the access excep­
tion for the inaccessible part is recognized.
Resulting Condition Code:
o Operands are equal
1 First operand is ,low 2 First operand is high
3 - Program Exceptions: Aecess (fetch, operand 2, CL and CLC; fetch,
operand 1, CLI and CLC) Programming Note
The COMPARE LOGICAL instruction treats all
bits alike as part of an unsigned binary quantity. In
variable-length operation, comparison may extend to
field lengths of 256 bytes. The operation may be
used to compare unsigned packed decimal fields or
alphameric information in any code that has a collat­
ing slequence based on ascending or descending bi­
nary values. For example, EBCDIC has a collating sequence based on ascending binary values. COJ'IIpare Logical Characters Under Mask
The second operand is compared with the first oper'- and, under control of a mask, and the result is indi­
cated in the condition code.
The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes,
left to right, of the general register designated by the
R 1 field. The byte positions corresponding to ones in
the mask are considered as a contiguous field and
126 System/370 Principles of Operation
are compared with the second operand. The second
operand is a contiguous field in storage, starting at
the second-operand address and equal in length to
the number of ones in the mask. The bytes in the
general register corresponding to zeros in the mask
do not participate in the operation.
The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The operation proceeds left to right.
When the mask is not zero, exceptions associated
with storage-operand access are recognized only for
the number of bytes specified by the mask. Howev­
er, when part of the designated storage operand is in
an inaccessible location but the operation can be
completed by using the accessible operand parts, it is
unpredictable whether the exception for the inaccess­
ible part is indicated. When the mask is zero, access
exceptions are recognized for one byte. Resulti,:" Condition Code:
o Selected bytes are equal, or mask is zero
1 Selected field of first operand is low
2 Selected field of first operand is high
3 -
Program Exceptions:
Access (fetch, operand 2)
Compare Logical Long
CLCL Rl,R2 [RR] OF o
The first operand is compared with the second oper­
and, and the result is indicated in the condition
code. The shorter operand is considered extended
with the padding character.
The Rl and R2 fields each specify an even-odd
pair of general registers and must designate an even­
numbered register; otherwise, a specification excep­
tion is recognized.
The location of the leftmost byte of the first oper­
and and second operand is designated by bits 8-31
of the general registers specified by the Rl and R2
fields, respectively. The number of bytes in the first­
operand and second-operand locations is specified
by bits 8-31 of the general registers having addresses
Rl + 1 and R2+ 1, respectively. Bit positions 0-7 of
register R2 + 1 contain the padding character. The
contents 01" bit positions 0-7 of registers Rl, R2, and
R 1 + 1 are ignored.
Graphically, the contents of the registers just de­
scribed are as follows:

R1 First-Operand Address I 0 8 31
R1 + 1 First-Operand Length 0 8
31
R2 Second-Operand Address 0 8 31
R2 + 1 I Pad Second-Operand Length 0 8 31
The comparison is performed with the operands
considered as binary unsigned quantities, with all
codes valid. The comparison starts at the high-order
end of both fields and proceeds to the right. The
operation ends as soon as an inequality is detected
or the end of the longer operand is reached. If the
operands are not of the same length, the shorter
operand is extended, for the purpose of comparison,
with the padding character.
If both operands are of zero length, the operands
are considered equal.
The execution of the instruction is interruptible.
When an interruption occurs after a unit of opera­
tion other than the last one, the contents of registers
R 1 + 1 and R2 + 1 are decremented by the number of
bytes compared, and the contents of registers Rl and
R2 are incremented by the same number, so that the
instruction, when re-executed, resumes at the point
of interruption. The high-order byte of registers Rl
and R2 is set to zero; the contents of the high-order
byte of registers Rl + 1 and R2+ 1 remain un­
changed; and the condition code is unpredictable. If
the operation is interrupted after the shorter operand
has been exhausted, the count field pertaining to the
shorter operand is zero, and its address is updated
accordingly.
If the operation ends' because of a mismatch, the
count and address fields at completion identify the
byte of mismatch. The contents of bit positions
8-31 of registers Rl + 1 and R2+ 1 are decremented
by the number of bytes that matched, unless the
mismatch occurred with the padding character, in
which case the count field for the shorter operand is
set to zero. The contents of bit positions 8-31 of
registers Rl and R2 are incremented by the ap:lounts by which the corresponding count fields were re­
duced. If the two operands, including the padding
character, if necessary, are equal, both count fields
are made zero at completion, and the addresses are
incremented by the corresponding count values. The
contents of bit positions 0-7 of registers Rl and R2
are set to zero, including the case when one or both
of the original count values are zero. The contents of
bit positions 0-7 of registers R 1 + 1 and R2 + 1 remain
unchanged.
When part of an operand is designated in an inac­
cessible location, but the operation can be completed
by using the available operand parts, it is unpredicta­
ble whether the access exception for the inaccessible
part is recognized.
When the count field for an operand has the value
zero, no access exceptions are recognized for that
operand.
Resulting Condition Code:
o Operands are equal, or both fields have zero
length
1 First operand is low
2 First operand is high
3 -
Program Exceptions:
Access (fetch, operands 1 and 2)
Specification
Programming Notes
When the contents of the R 1 and R2 fields are the
same, condition code 0 is set, and protection and
addressing exceptions are indicated when called for
by the operand designation. Special precautions should be taken when COM­ P ARE LOGICAL LONG is made the subject of
EXECUTE. See the programming notes under EX­
ECUTE. See also the programming notes under MOVE LONG.
Convert to Binary CVB [RX]
4F
o 8 12 16 20 The radix of the second operand is changed from
decimal to binary, and the result is placed in the
first-operand location. The number is treated as a
right-aligned signed integer both before and after
conversion.
31
The second operand has the packed decimal data
format and is checked for valid sign and digit codes.
Improper codes are a data exception and cause a
General Instructions 127