program interruption. The decimal operand occupies
eight bytes in storage. The low-order four bits of the
field represent the sign. The remaining 60 bits con­
tain 15 binary-coded-decimal digits in true notation.
The packed decimal data format is described under
"Decimall Instructions."
The result of the conversion is placed in the gen­
eral register specified by Rt. The maximum number
that can be converted and still be contained in a
32-bit register is 2,147,483,647; the minimum num­
ber is -2,147,483,648. For any decimal number out­
side this range, the operation is completed by placing
the 32 low-order binary bits in the register; a fixed­
point divide exception exists, and a program inter­
ruption follows. In the case of a negative second
operand, the low-order part is in two's-complement
notation.
Conditioll' Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2)
Data
Fixed-Point Divide
Converlr to Decimal CVD o 8 12 16
[RX] 20 31
The radix of the first operand is changed from bina­
ry to decimal, and the result is stored in the second­
operand location. The number is treated as a right­
aligned signed integer both before and after conver­
sion.
The result is placed in the storage location desig­
nated by the second operand and has the packed
decimal format, as described in "Decimal Instruc­
tions." The result occupies eight bytes in storage.
The low-order four bits of the field represent the
sign. A positive sign is encoded as 1100; a negative
sign is eneoded as 1101. The remaining 60 bits con­
tain 15 binary-coded-decimal digits in true notation.
The number to be converted is obtained as a 32-
bit signed integer from a general register. Since 15
decimal digits are available for the decimal equiva­
lent of 31 bits, an overflow cannot occur.
Condition Code:
The code remains unchanged.
128 System/370 Principles of Operation Program Exceptions: ,Access (store, operand 2)
Divide
DR Rt,R2 [RR]
10 R1 I R2 I 0 8 12 15
D R t ,D2(X2,B2) [RX]
50 I R, I X
2 I B2 0 8 12 16 I O
2 I 20 31
The dividend (first operand) is divided by the divisor
(second operand) and replaced by the remainder and
the quotient.
The dividend is a 64-bit signed integer and occu­
pies the even-odd pair of registers specified by the
Rt field of the instruction. A specification exception
occurs when Rt is odd. A 32-bit signed remainder
and a 32-bit signed quotient replace the dividend in
the even-numbered and odd-numbered registers,
respectively. The divisor is a 32-bit signed integer.
The sign of the quotient is determined by the
rules of algebra. The remainder has the same sign as
the dividend, except that a zero quotient or a zero
remainder is always positive. When the relative mag­
nitude of dividend and divisor is such that the quo­
tient cannot be expressed by a 32-bit signed integer,
a fixed-point divide exception is recognized (a pro­
gram interruption occurs, no division takes place,
and the dividend remains unchanged in the general
registers).
Condition Code:
The code remains unchanged.
Program Exceptions:
Access (fetch, operand 2 of D only)
Specification
Fixed-Point Divide
Exclusive OR XR [RR]
17
o 8 12 15

x
o
XI
o
xc
o
8 12 16 20 [SI]
97
8
Dl(L,Bl),D2(B2)
07 L
8
16 20 [SS]
31
31
The EXCLUSIVE OR of the first and second.oper­
ands is placed in the first-operand location. Operands are treated as unstructured logical
quantities, and the connective EXCLUSIVE OR is
applied bit by bit. A bit position in the result is set to
one if the corresponding bit positions in the two
operands are unlike; otherwise, the result bit is set to
zero.
For XC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Resulting Condition Code:
o Result is zero
1 Result not zero
2 -
3 -
Program Exceptions:
Access (fetch, operand 2, X and XC; fetch and
. store, operand 1, XI and XC)
Programming Note
The instruction EXCLUSIVE OR may be used to
invert a bit, an operation particularly useful in test­
ing and setting programmed binary bit switches.
A field EXCLUSIVE-ORed with itself becomes
all zeros.
The sequence A EXCLUSIVE-ORed B, B EXCLUSIVE-ORed A, A EXCLUSIVE-ORed B
results in the exchange of the contents of A and B
without the use of an auxiliary buffer area.
The execution of XI and XC consists in fetching a
first-operand byte from main storage and subse­
quently storing the updated value. These fetch and
store accesses to a particular byte do not necessarily
occur one immediately after the other. Thus, the
Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
instruction EXCLUSIVE OR cannot be safely used
to update a shared location in main storage if the
possibility exists that another CPU or a channel
may also be updating the location. For XI, only one
byte is stored.
Execute
44
o 8 12 16 20 31
The single instruction at the second-operand address
is modified by the contents of the general register
specified by Rl, and the resulting subject instruction
is executed.
Bits 8-15 of the instruction designated by the
branch address are ORed with bits 24-31 of the reg­
ister specified by Rl, except when register 0 is speci­
fied, which indicates that no modification takes
place. The subject instruction may be two, four, or
six bytes in length. The ORing does not change ei­
ther the contents of the register specified by Rl or
the instruction in storage, and it is effective only for
the interpretation of the instruction to be executed.
The execution and exception handling of the sub­
ject instruction are exactly as if the subject instruc­
tion were obtained in normal sequential operation,
except for the instruction address and the
instruction-length code.
The instruction address of the current PSW is
increased by the length of EXECUTE. This updat­
ed address and the length code (2) of EXECUTE
are used as part of the link information when the
subject instruction is BRANCH AND LINK. When
the subject instruction is a successful branching in­
struction, the updated instruction address of the
current PSW is replaced by the branch address speci­
fied by the subject instruction.
When the subject instruction is in turn an EXE -
CUTE, an execute exception is recognized, and the
operation is suppressed. The effective address of
EXECUTE must be even; otherwise, a specification
exception is recognized.
Condition Code:
The code may be set by the subject instruction. Program Exceptions:
Execute
Access (fetch, operand 2)
Specification
General Instructions 129