x
o
XI
o
xc
o
8 12 16 20 [SI]
97
8
Dl(L,Bl),D2(B2)
07 L
8
16 20 [SS]
31
31
The EXCLUSIVE OR of the first and second.oper­
ands is placed in the first-operand location. Operands are treated as unstructured logical
quantities, and the connective EXCLUSIVE OR is
applied bit by bit. A bit position in the result is set to
one if the corresponding bit positions in the two
operands are unlike; otherwise, the result bit is set to
zero.
For XC, each operand field is processed left to
right. When the operands overlap, the result is ob­
tained as if the operands were processed one byte at
a time and each result byte were stored immediately
after the necessary operand byte is fetched.
Resulting Condition Code:
o Result is zero
1 Result not zero
2 -
3 -
Program Exceptions:
Access (fetch, operand 2, X and XC; fetch and
. store, operand 1, XI and XC)
Programming Note
The instruction EXCLUSIVE OR may be used to
invert a bit, an operation particularly useful in test­
ing and setting programmed binary bit switches.
A field EXCLUSIVE-ORed with itself becomes
all zeros.
The sequence A EXCLUSIVE-ORed B, B EXCLUSIVE-ORed A, A EXCLUSIVE-ORed B
results in the exchange of the contents of A and B
without the use of an auxiliary buffer area.
The execution of XI and XC consists in fetching a
first-operand byte from main storage and subse­
quently storing the updated value. These fetch and
store accesses to a particular byte do not necessarily
occur one immediately after the other. Thus, the
Page of GA22-7000-4
Revised September 1, 1975
By TNL: GN22-0498
instruction EXCLUSIVE OR cannot be safely used
to update a shared location in main storage if the
possibility exists that another CPU or a channel
may also be updating the location. For XI, only one
byte is stored.
Execute
44
o 8 12 16 20 31
The single instruction at the second-operand address
is modified by the contents of the general register
specified by Rl, and the resulting subject instruction
is executed.
Bits 8-15 of the instruction designated by the
branch address are ORed with bits 24-31 of the reg­
ister specified by Rl, except when register 0 is speci­
fied, which indicates that no modification takes
place. The subject instruction may be two, four, or
six bytes in length. The ORing does not change ei­
ther the contents of the register specified by Rl or
the instruction in storage, and it is effective only for
the interpretation of the instruction to be executed.
The execution and exception handling of the sub­
ject instruction are exactly as if the subject instruc­
tion were obtained in normal sequential operation,
except for the instruction address and the
instruction-length code.
The instruction address of the current PSW is
increased by the length of EXECUTE. This updat­
ed address and the length code (2) of EXECUTE
are used as part of the link information when the
subject instruction is BRANCH AND LINK. When
the subject instruction is a successful branching in­
struction, the updated instruction address of the
current PSW is replaced by the branch address speci­
fied by the subject instruction.
When the subject instruction is in turn an EXE -
CUTE, an execute exception is recognized, and the
operation is suppressed. The effective address of
EXECUTE must be even; otherwise, a specification
exception is recognized.
Condition Code:
The code may be set by the subject instruction. Program Exceptions:
Execute
Access (fetch, operand 2)
Specification
General Instructions 129
Programming Notes
The ORing of eight bits from the general register
with the designated instruction permits indirect
length, index, mask, immediate data, and arithmetic­
register specification.
If the subject instruction is a successful branch,
the length code still stands at 2.
An addressing or specification exception may be
caused by EXECUTE or by the subject instruction.
When an interruptible instruction is made a sub­
ject of EXECUTE, the program normally should not
designate any register updated by the interruptible
instruction as either the Rl, X2, or B2 register for EXECUTE, since on resumption of execution after
an interruption, or if the instruction is refetched
without an interruption, the updated values of these
registers will be used in the execution of EXECUTE.
Similarly, the program should normally not let the
destination field of an interruptible instruction in­
clude the location of the EXECUTE, since the new
contents of the location may be interpreted for a
resumption of the execution.
Insert Character
[RX]
The byte at the second-operand location is inserted
into bit positions 24-31 of the general register desig­
nated by the Rl field. The remaining bits in the reg­
ister remain unchanged. ContJ'ition COde: The code remains unchanged. Exceptions: Aecess (fetch, operand 2)
Inse'rt Characters Under Mask
Bytes from contiguous locations beginning at the
second-operand address are inserted into the first­ operand location under control of a mask.
31 The contents of the M3 field, bit positions 12-15,
are used as a mask. The four bits of the mask, left to
right, correspond one for one with the four bytes, 130 System/370 Principles of Operation left to right, of the general register designated by the
Rl field. The byte positions corresponding to ones in
the mask are filled, in the order of ascending byte
numbers, with bytes from the storage operand. Bytes
are fetched from contiguous storage locations begin­
ning at the second-operand address. The length of
the second operand is equal to the number of ones in
the mask. The bytes in the general register corre­
sponding to zeros in the mask remain unchanged.
The resulting condition code is based on the mask
and on the value of the bits inserted. When the mask
is zero or when all inserted bits are zero, the condi­
tion code is made O. When all inserted bits are not
zero, the code is set according to the leftmost bit of
the storage operand: if this bit is one, the code is
made 1 to indicate a negative algebraic value; if this
bit is zero, the code is made 2, reflecting a positive
algebraic value.
When the mask is not zero, exceptions associated
with storage operand access are recognized only for
the number of bytes specified by the mask. When
the mask is zero, access exceptions are recognized
for one byte.
Resulting Condition Code:
o All inserted bits are zeros, or mask is zero
1 First bit of the inserted field is one
2 First bit of the inserted field is zero, and not all
inserted bits are zeros
3 -
Program Exceptions:
Access (fetch, operand 2)
Programming Note
The condition code for INSERT CHARACTERS
UNDER MASK is defined such that when the mask
is 1111, the instruction causes the same condition
code to be set as for LOAD AND TEST.
Load
[RR]
o 8 12 15
L [RX]
58
o 8 12 16 20 31
The second operand is placed unchanged in the first­
operand location.
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