Channel Model Number
o 4
Maximum IOEL Length
31
Bits 0-3 specify the channel type. When a channel
can operate as more than one type, the code stored
identifies the channel type at the time the instruction
is executed. The following codes are assigned: 0000 Selector 0001 Byte multiplexer 0010 Block multiplexer
Bits 4-15 identify the channel model. When the
channel model is implied by the channel type and the CPU model, zeros are stored in the field.
Bits 16-31 contain the length in bytes of the long­
est I/O extended logout that can be stored by the
channel during an I/O interruption. If the channel
never stores logout information using the 10EL pointer, then this field is set to zero.
When the channel detects an equipment malfunc­
tion during the execution of STORE CHANNEL
ID, the channel causes the status portion, bits 32-47,
of the CSW to be replaced by a new set of status
bits. With the exception of the channel control check
bit (bit 45), which is stored as a one, all bits in the
status field are stored as zeros. The contents of the
other fields of the CSW are not changed.
When STORE CHANNEL ID cannot be execut­
ed because of a pending logout condition which af­
fects the operational capability of the channel, a full CSW is stored. The fields in the CSW are all set to
zero, with the exception of the logout-pending bit
and the channel control check bit, which are set to
ones. No channel logout is associated with this sta­
tus.
Program Exceptions:
Privileged operation
Resulting Condition Code:
o Channel ID correctly stored
1 CSW stored
2 Channel activity prohibited storing ID
3 Not operational
The condition code set by STORE CHANNEL
ID for all possible states of the I/O system is shown
graphically as follows. See "States of the
Input/ Output System" for a detailed definition of
the A, I, W, and N states.
A W N
Channel
o $ $ 3
A Available I Interruption pending
W Working
N
Not operational
$ When the channel is unable to store the channel 10 because
of its working state or because it contains a pending inter­ ruption condition, a condition code 2 is set. If the working
or interruption pending state does not preclude the storing
of the channel ID, a condition code 0 is set.
Condition Codes Set by STORE CHANNEL ID
Test Channel
TCH [S] 9FOO o 16 20 31
The condition code in the PSW is set to indicate the
state of the addressed channel. The state of the
channel is not affected, and no action is caused. Bits
8-15 of the instruction are ignored.
The instruction TEST CHANNEL is executed
only when the CPU is in the supervisor state.
Bits 16-23 of the second-operand address identify
the channel to which the instruction applies. Bit posi­
tions 24-31 of the address are ignored.
The instruction TEST CHANNEL inspects only
the state of the addressed channel. It tests whether
the channel is operating in the burst mode, is aware
of any outstanding interruption conditions from its
devices, or is not operational. When the channel is
operating in the burst mode and contains a pending
interruption condition, the condition code is set as
for operation in the burst mode. When none of these
conditions exist, the available state is indicated. No
device is selected and, on the multiplexer channel,
the sub channels are not interrogated.
Program Exceptions:
Privileged operation
Resulting Condition Code:
o Channel available
1 Interruption or logout condition pending in
channel
2 Channel operating in burst mode
3 Channel not operational
The condition code set by TEST CHANNEL for
all possible states of the addressed channel is shown
Input/Output Operations 207

graphically as follows. See "States of the
Input/Output System" for a detailed definition of
the A, I, W, and N states. Channel A W N
o 2 3
A Available I Intenruption pending
W Working
N
Not ()perational Condition Codes Set by TEST CHANNEL Test I/O TIO [S] IB2 31 9000 The state of the addressed channel, subchannel, and
device is indicated by setting the condition code in
the PSW and, under certain conditions, by storing
the CSW. Pending interruption conditions may be
cleared. Bits 8-14 of the instruction are ignored.
The instruction TEST I/O is executed only when
the CPU is in the supervisor state.
Bits 16-31 of the second-operand address identify
the channel, subchannel, and I/O device to which
the instruction applies.
The TIO function is performed by the instruction TEST I/O and, on some channels and under certain
circumstances, by CLEAR I/O. When the channel is operating in burst mode and
the addressed sub channel contains a pending inter­
ruption condition, the TIO function causes condition
code 1 or 2 to be set, depending on the channel type
and system model. If condition code 1 is set, the CSW is stored at location 64 to identify the interrup­
tion condition, and the interruption condition is
cleared.
When the condition in the following paragraph
occurs with the channel either available or in the
interruption pending state, or, on some channels, in
the working state, the TIO function causes the CSW to be stored. The contents of the entire CSW pertain
to the I/O device addressed by the instruction.
The sub channel contains a pending interrup­
tion condition due to a terminated operation at
the addressed device. The CSW identifies the
interruption condition, and the interruption
condition is cleared. The protection key, com­
mand address, and count fields contain the fi- 208 System/370 Principles of Operation nal values for the I/O operation, and the status
may include other bits provided by the channel
and the device. The interruption condition in
the sub channel is not cleared, and the CSW is
not stored if the channel is in the working state
and has not yet accepted the interruption con­
dition from the device.
When any of the following conditions occurs with
the channel either available or in the interruption­
pending state, the TIO function causes the CSW to
be stored. The contents of the entire CSW pertain to
the I/O device addressed by the instruction.
1. The sub channel is available, and the I/O device
contains a pending interruption condition or the control unit contains a pending control unit
end for the addressed device. The CSW unit­ status field identifies the interruption condition
and may contain other bits provided by the
device or control unit. The interruption condi­
tion is cleared. The busy bit in the CSW is off.
The other fields of the CSW contain zeros un­
less an equipment error is detected.
2. The sub channel is available, and the I/O device
or the control unit is executing a previously
initiated operation or the control unit has a
pending interruption condition associated with
a device other than the one addressed. The CSW unit-status field contains the busy bit or,
if the control unit is busy, the busy and status
modifier bits. Other fields of the CSW contain
zeros unless an equipment error is detected.
3. The subchannel is available, and the I/O device
or channel detected an equipment error during
execution of the instruction or the addressed
device is in the not-ready state and does not
have any pending interruption condition. The CSW identifies the error conditions. If the de­
vice is not ready, unit check is indicated. No
interruption conditions are generated at the I/O device or the sub channel.
When TEST I/O cannot be executed because of a
pending logout condition which affects the opera­
tional capability of the channel or subchannel, a full CSW is stored. The fields in the CSW are all set to
zeros, with the exception of the logout-pending bit
and the channel-control-check bit, which are set to
ones. No channel logout is associated with this sta­
tus.
When the TIO function is used to clear an inter­
ruption condition from the sub channel and the chan­
nel has not yet accepted the condition from the de­
vice, the function causes the device to be selected
and the interruption condition in the device to be
cleared. During certain I/O operations, some types
of devices cannot provide their current status in re-