sponse to TEST I/O. Some tape control units, for
example, are in such a state when they have provid­
ed the channel end condition and are executing the
backspace-file operation. When TEST I/O is issued
to a control unit in such a state, the unit-status field
of the CSW contains the busy and status modifier
bits, with zeros in the other CSW fields. The inter­
ruption condition in the device and in the subchan­
nel is not cleared. On some types of devices, such as the 2702 Transmission Control, the device never provides its
current status in response to TEST I/O, and an in­
terruption condition can be cleared only by permit­
ting an I/O interruption. When TEST. I/O is issued
to such a device, the unit-status field contains the
status modifier bit, with zeros in the other CSW
fields. The interruption condition in the device and
in the subchannel, if any, is not cleared.
However, at the time the channel assigns the
highest priority for interruptions to a condition asso­
ciated with an operation at the subchannel, the chan­
nel accepts the status from the device and clears the
corresponding condition at the device. When the 'flO function is addressed to a device for which the
channel has already accepted the interruption condi­
tion, the device is not selected, and the condition in
the sub channel is cleared regardless of the type of
device and its present state. The CSW contains unit
status and other information associated with the
interruption condition. On the byte-multiplexer channel, the TIO func­
tion causes the addressed device to be selected only
after the channel has serviced all outstanding re-
A Channel A ,Ii: 11# , W , N, Subchannel 2 1* 2 3 Control Unit ,A I I ,W, N AI or Device 0 1 * 1 * 3 0 A Available I nterru ption pendi ng
A
quests for data transfer for previously initiated opera­
tions.
Program Exceptions: Privileged operation
Resulting Condition Code:
o Available
1 CSW stored
2 Channel or sub channel busy
3 Not operational
The condition code set by the TIO function for all
possible states of the I/O system is shown graphical­
ly as follows. See "States of the Input/Output Sys­ tem" for a detailed definition of the A, I, W, and N
states.
Programming Notes
Disabling the CPU for I/O interruptions provides
the program a means of controlling the priority of I/O interruptions selectively by channels. The priori­
ty of devices attached on a channel is fixed and can­
not be controlled by the program. The instruction
TEST I/O permits the program to clear interruption
conditions selectively by I/O device.
When a CSW is stored by the TIO function, the
interface-control-check and channel-control-check
indications may be due to a condition already exist­
ing in the channel or due to a condition created by
the TIO function. Similarly, presence of the unit
check bit in the absence of channel end, control unit
end, or device end bits may be due to a condition
created by the preceding operation, the not-ready Wi: I
W
#, N
2 3 ,Ii: ,1# , W
N
A 13 2 1* 2 2 2 @ 2 2 I I W ,N , 1 * 1 * 3 Ii: Interruption pending for a device other than the one addressed 1# I nterruption pending for the addressed device
W Working Wi: Working with a device other than the one addressed
W# Working with the addressed device
N
Not operational CSW stored
@ In the Wi: I #X state, either condition code 1 may be set with the CSW stored, or condition
code 2 may be set, depending on the channel and the conditions in the channel. Note: Underscored condition codes pertain to conditions that can occur only on the multiplexer channel. Condition Codes Set by TEST I/O Input/Output Ope.rations 209

state, or an equipment error detected during the
execution of TEST I/O. The instruction TEST I/O cannot be used to clear a pending interruption condi­
tion due t.o the PCI flag while the subchannel is in
the working state.
Input/{)utput Instruction Exception
Handling
Before the channel is signaled to execute an I/O instruction, the instruction is tested for validity by
the CPU. Exceptional conditions detected at this
time cause a program interruption. When the inter­
ruption occurs, the current PSW is stored as the pro­
gram old PSW and is replaced by the program new PSW. The interruption code in the old PSW identi­
fies the cause of the interruption.
The following exception may cause a program
interruption:
Privileged Operation: An I/O instruction is encoun­
tered when the CPU is in the problem state. The
instruction is suppressed before the channel has been
signaled to execute it. The CSW, the condition code
in the PSW, and the state of the addressed sub chan­
nel and I/O device are not affected by the attempt
to execute an I/O instruction while in the problem
state.
Execution of Input/Output Operations The channel can execute six commands: write,
read, read backward, control, sense, and transfer in
channel. Each command except transfer in channel
initiates a corresponding I/O operation. The term "I/O operation" refers to the activity initiated by a
command in the I/O device and associated subchan­
nel. The subchannel is involved with the execution
of the operation from the initiation of the command
until the channel-end signal is received or, in the
case of command chaining, until the device-end sig­
nal is received. The operation in the device lasts until
device end occurs.
Blocking of Data
Data recorded by an I/O device may be divided into
blocks. The length of a block depends on the device;
for example, a block can be a card, a line of printing,
or the information recorded between two consecu­
tive gaps on magnetic tape.
The maximum amount of information that can be
transferred in one I/O operation is one block. An I/O operation is terminated when the associated
main storage area is exhausted or the end of the
block is reached, whichever occurs first. For some
operations, such as writing on a magnetic tape unit 210 Syste:m/370 Principles of Operation or at an inquiry station, blocks are not defined, and
the amount of information transferred is controlled
only by the program.
Channel Address Word
The channel address word ( CAW) specifies the stor­
age protection key and the address of the first CCW
associated with ST ART I/O or START I/O FAST RELEASE. The channel refers to the CAW only
during the execution of START I/O or START I/O FAST RELEASE. The CAW is fetched from real
location 72 of the CPU issuing the instruction. The
pertinent information thereafter is stored in the sub­
channel, and the program is free to change the con­
tents of the CAW. Fetching of the CAW by the
channel does not affect the contents of the location.
The CAW has the following format: I Key CCW Address
o 4 8
The fields in the CAW are allocated for the fol­
lowing purposes:
31
Protection Key: Bits 0-3 form the protection key for
all commands associated with ST ART I/O and ST ART I/O FAST RELEASE. This key is matched
with a key in storage whenever a reference is made
to main storage during an I/O operation.
CCW Address: Bits 8-31 designate the location of
the first CCW in absolute main storage.
Bit positions 4-7 of the CAW must contain zeros.
The three low-order bits of the command address
must bc zeros to specify the CCW on integral
boundaries for doublewords. If any of these restric­
tions is violated or if the CCW address specifies a
location protected against fetching or outside the
main storage of the particular installation, ST ART
II 0 and ST ART I/O FAST RELEASE cause the
status portion of the CSW to be stored with the pro­
tection check or program-check bit on. In this event,
the I/O operation is not initiated.
Programming Note
Bit positions 4-7 of the CAW, which presently must
contain zeros, may in the future be assigned for the
control of new functions. It is therefore recommend­
ed that these bit positions not be set to one for the
purpose of obtaining an intentional program-check
indication.