parameters in control registers 0 and 1, intro­
ducing invalid values in bit positions 0-7 of an
Ee PSW). For situations 1 and 2, the operation is nullified,
and the instruction designated by the instruction
address is the same as the last one executed. These
two are the only ca'ses where the instruction address
in the old PSW identifies the instruction causing the
exception.
For situations 3, 4, and 5, the instruction address
in the prlOgram old PSW has been replaced and can­
not be calculated using the one appearing in the PSW. For situation 6, the logical instruction address in
the PSW has not been replaced, but the correspond­
ing real address after the change is different.
When bit 8 (program event) in the interruption
code is on, the PER address at locations 153-155
identifies the location of the instruction causing the
interruption, and the instruction-length code OLC) is redundant. Similarly, the ILC is redundant when
the operation is nullified, since in this case the ILC
can be derived from the operation code of the in­
struction identified by the old PSW. Point 01 Interr.llption An interruption is permitted between that is, an interruption can occur after the perform­
ance of one operation and before the start of a sub­
sequent operation. The entire execution of an in­
struction is an operation.
For the two instructions MOVE LONG and COMPAlRE LOGICAL LONG, referred to as inter­
ruptible instructions, an interruption is permitted
after a partial execution of the instruction. The exe­
cution of an interruptible instruction is considered to
consist of a number of units of operation, and an
interruption is permitted between units of operation.
The amount of data processed in a unit of operation
depends on the particular instruction and may de­
pend on the model and on the particular condition
that causes the execution of the instruction to be
interrupted.
Whenever discussion in this publication pertains
to points IOf interruptibility that include those occur­
ring within the execution of an interruptible instruc­
tion, the term "unit of operation" is used. This use
of the term considers that the entire execution of the
noninterrnptible instruction consists, in effect, of
one unit of operation.
Programming Note
Any interruption, other than supervisor call and
some program interruptions, can occur after a partial
execution of an interruptible instruction. In pa:rticu-
74 System/370 Principles of Operation lar, interruptions for I/O, external, and machine­
check conditions and for program access exceptions
can occur between units of operation.
Instruction Execution
Types of Ending
Instruction execution is said to end in one of four
ways--completion, nullification, suppression, and
termination.
When the execution of an instruction is complet­
ed, results are provided as called for in the definition
of the instruction. When an interruption occurs after
the completion of the execution of an instruction,
the instruction address in the old PSW designates the
next instruction to be executed" When the execution of an instruction is sup­
pressed, the instruction is executed as if it specified "no operation." The contents of any result fields,
including the condition code, are not changed. The
instruction address in the old PSW on an interrup­
tion after suppression designates the next sequential
instruction.
Nullification is the same as suppression, except
that when an interruption occurs after the execution
of the instruction has been nullified, the instruction
address in the old PSW designates the instruction
whose execution was nullified instead of the next
sequential instruction.
When the execution of an instruction is terminat­
ed, the contents of any fields due to be changed by
the instruction are unpredictable. The operation may
have replaced all, part, or none of the contents of
the designated result fields and may have changed
the condition code if such change was called for by
the instruction. Unless the interruption is caused by
a machine-check condition, the validity of the in­
struction address in the PSW, the interruption code,
and the instruction-length code are not affected; and
the state or the operation of the system has not been
affected in any other way. The instruction address in
the old PSW on an interruption after termination
designates the next sequential instruction.
Execution of Interruptible Instructions
The execution of an interruptible instruction is com­
pleted when all units of operation associated with
that instruction are completed. When an interruption
occurs after completion, nullification, or suppression
of a unit of operation, all prior units of operation
have been completed. On completion of a unit of operation other than
the last one and on nullification of any unit of opera­
tion, the instruction address in the old PSW desig­
nates the interrupted instruction, and the operand

parameters are adjusted such that the execution of
the interrupted instruction is resumed from the point
of interruption when the old PSW stored on the in­
terruption is made the current PSW. It depends on
the instruction how the operand parameters are ad­
justed.
When a unit of operation is suppressed, the in­
struction address in the old PSW designates the next
sequential instruction. The operand parameters,
however, are adjusted so as to indicate the extent to
which instruction execution has been completed. If
the instruction is reexecuted after the conditions
causing the suppression have been removed, the
execution is resumed from the point of interruption.
As in the case of completion and nullification, it
depends on the instruction how the operand parame­
ters are adjusted.
When a unit of operation of an interruptible in­
struction is terminated, the contents, in general, of
any fields due to be changed by the instruction are
unpredictable. On an interruption, the instruction
address in the old PSW designates the next sequen­
tial instruction.
Machine-Check Interruption
The machine-check interruption provides a means
for reporting to the program the oc-currence of
equipment malfunctions. Information is provided to
assist the program in determining the location of the
fault and extent of the damage.
A machine-check interruption causes the old PSW to be stored at location 48 and a new PSW to be
fetched from location 112. When the old PSW spec­
ifies the BC mode, the interruption code and the
instruction-length code in the old PSW are unpredict­
able.
The cause and severity of the malfunction are
identified by a 64-bit machine-check code stored at
location 232. Further information identifying the
cause of the interruption and the location of the fault
may be stored at locations 216-511 and in the area
starting with the location designated by the contents
of control register 15.
Interruption action and the storing of the associ­
ated information are under the control of PSW bit
13 and bits in control register 14. See the chapter
"Machine-Check Handling" for more detailed in­
formation.
Program Interruption
Exceptions resulting from execution of the program,
including the improper specification or use of in­
structions and data, or the detection of a program or
monitor event cause a program interruption. A program interruption causes the old PSW to be
stored at location 40 and a new PSW to be fetched
from location 104. The cause of the interruption is identified by the
interruption code. When the old PSW specifies the
BC mode, the interruption code and the instruction­
length code are placed in the old PSW; when it speci­
fies the EC mode, the interruption code is placed at
locations 142-143, the instruction-length code is
placed in bit positions 5 and 6 of the byte at location
141, with the rest of the bits set to zero, and zeros
are stored at location 140. For some causes addition­
al information identifying the reason for the inter­
ruption is stored in main-storage locations 144-159.
Except for the program-event condition, the con­
dition causing the interruption is identified by a cod­
ed value placed in the rightmost seven bit positions
of the interruption code. Only one condition at a
time can be indicated. Bits 0-7 of the interruption
code are set to zeros.
The program-event condition is indicated by set­
ting bit 8 of the interruption code to one, with bits 0- 7 set to zeros. A program-event condition can be
indicated concurrently with another program inter­
ruption condition, in which case bit 8 is one and the
coded value appears in bit positions 9-15.
A program interruption can occur only when the
corresponding mask bit, if any, is one. The program
mask in the PSW permits masking four of the excep­
tions, bit 1 in control register 0 controls whether SET SYSTEM MASK causes a special-operation
exception, bits 16-31 in control register 8 control
interruptions due to monitor events, and, in the EC
mode, masks are provided for controlling interrup­
tions due to program events. When the mask bit is
zero, the condition is ignored; the condition does not
remain pending.
Programming Note
When the new PSW for a program interruption has 11 format error or causes an exception to be recognized
in the process of instruction fetching, a string of
program interruptions takes place. See "Priority of
Interruptions" for a description of how such strings
are terminated. Some of the conditions indicated as program ex­
ceptions may be recognized also by an I/O opera­
tion, in which case the exception is indicated in the
channel status word.
Program Interruption Conditions
The following is a detailed description of each
program-interruption condition.
Interruptions 75