Operation Exception
An operation exception is recognized when the CPU encounters an instruction with an invalid operatIOn
code. The operation code may not be assigned, or
the instruction with that operation code may not be
available on the CPU. For the purpose of recogniz­
ing an operation exception, the first eight bits of an
instruction, or, when the first eight bits have the
hexadecimal value B2, the first 16 bits form the oper­
ation code.
The operation is suppressed.
The instruction-length code is 1,2, or 3.
Programming Note
In the case of I/O instructions with the values 9C,
9D, and 9E in bit positions 0-7, the value of bit 15 is
used to distinguish between two instructions. Bits
8-14, however, are not checked for zeros, and these
operation codes never cause an operation exception
to be recognized.
To ensure that presently written programs run if
and when the operation codes 9C, 9D, and 9E are
extended further to provide for new functions, only
zeros should be placed in bit positions 8-14. Similar­
ly, zeros should be placed in bit positions 8-15 in the
instruction with the operation code 9F. In accord­
ance with these recommendations, the operation
codes for the seven I/O instructions are shown as 9COO, 9COl, 9DOO, 9DOl, 9EOO, 9EOl, and 9FOO. Some models may offer instructions not listed in
this manual, such as those provided for emulat.ion or
as part of special or custom features. Consequently,
all unlisted operation codes do not necessarily cause
an operation exception to be recognized. Further­
more, as part of the specified operation, these in­
structions may cause modes of operation to be set up
or otherwise alter the system so as to affect the ex­
ecution of subsequent instructions. In order to avoid
the possibility of accidentally causing such operation,
instructions with an unlisted operation code should
be issued only when the specific function associated
with the operation code is desired.
The operation code 00, with a two-byte instruc­
tion format, and the set of sixteen 16-bit operation
codes B2EO to B2EF, with a four-byte instruction
format, allocated for software uses where indica­
tion of invalid operation is required. It is improbable
that these operation codes will ever be assigned to
an instruction implemented in the CPU. Privileged-·Operation Exception
A privileged-operation exception is recognized when
the CPU encounters a privileged instruction in the
problem state.
The operation is suppressed.
76 System/370 Principles of Operation The instruction-length code is 1 or 2.
Execute Exception
The execute exception is recognized when the sub­
ject instruction of EXECUTE is another EXH­ CUTE. The operation is suppressed.
The instruction-length code is 2.
Protection Exception
A protection exception is recognized when the CPU causes a reference to a main-storage location that is
protected against the type of reference, and the key
in storage associated with the location does not
match the protection key in the PSW. The execution of the instruction is suppressed
when the location of the instruction, including the
location of the subject instruction of EXECUTE, is
protected against fetching. Except for some specific
instructions whose execution is suppressed, the oper­
ation is terminated when a protection exception is
encountered during a reference to an operand loca­
tion. See the following table for a summary of the
action taken on a protection exception. On fetching, the protected information is not
loaded into an addressable register or moved to an­
other storage location. When part of an operand
location is protected against storing and part is not,
storing may be performed in the unprotected part.
The contents of a protected location remain un­
changed.
For a protected operand location, the instruction­
length code is 1, 2, or 3, designating the length of
the instruction that caused the reference. However,
for a store-protected operand location, the
instruction-length code on some models may be O. When the location of any part of the instruction is
protected against fetching, the instruction-length
code is 1, 2, or 3, indicating the number of halfwords
by which the instruction address has been incre­
mented. It is unpredictable whether the code is 1, 2,
or 3.
Addressing Exception
An addressing exception is recognized when the CPU causes a reference to a main-storage location
that is not available to the CPU. A main-storage
location is not available to the CPU when the loca­
tion is not provided, when the storage unit is not
configured to the CPU, or when power is off in the
storage unit. An address designating an unavailable
storage location is referred to as invalid.
The execution of the instruction is suppressed
when the address of the instruction, including the
location of the subject instruction of EXECUTE, is

invalid. Similarly, the unit of operation is suppressed
when the exception is encountered during an implicit
reference to a dynamic-address-translation (DAT)
table entry Except for some specific instructions
whose execution is suppressed, the operation is ter­
minated for an operand address that can be translat­
ed but designates an unavailable location. See the
following table for a summary of the action taken on
an addressing exception.
Data in storage remains unchanged unless the
location is available to the CPU. When part of an
operand location is available to the CPU and part is
not, storing may be performed in the available part.
For an invalid operand address or an invalid ad­
dress of a DAT table entry associated with an oper­
and reference, the instruction-length code is 1, 2, or
3, designating the length of the instruction that
caused the reference. However, when the exception
is due to an attempt to store and the address can be
translated but designates an unavailable operand
location, the code on some models may be O. When any part of the location of an instruction is
unavailable or the address of a DAT table entry as­
sociated with an instruction fetch is invalid, the
instruction-length code is 1, 2, or 3, indicating the
number of halfword locations by which the instruc­
tion address has been incremented. It is unpredicta­
ble whether the code is 1, 2, or 3.
Specification Exception
A specification exception is recognized for the fol­
lowing causes:
1. An instruction address does not designate a
location on an even-byte boundary.
2. An operand address does not designate an inte­
gral boundary in an instruction requiring such
integral boundary designation.
3. The block address in SET STORAGE KEY or INSERT STORAGE KEY does not have zeros
in the four low-order bit positions.
4. An odd-numbered general register is designat­
ed by an R field of an instruction that requires
an even-numbered register designation.
5. A floating-point register other than 0, 2, 4, or 6
is specified for a short or long operand, or a
floating-point register other than 0 or 4 is speci­
fied for an extended operand.
6. The multiplier or divisor in decimal arithmetic
exceeds 15 digits and sign.
7. The first-operand field is shorter than or equal
to the second-operand field in decimal multipli­
cation or division.
8. Bit positions 8-11 of MONITOR CALL do not
contain zeros.
9. The EC mode is specified (PSW bit 12 is one)
in a CPU that does not have the EC facility
installed. 10. A one is introduced into an unassigned bit
position of the EC-mode PSW (bit positions 0, 2-4,16-17,24-39).
The execution of the instruction identified by the
old PSW is suppressed. However, for causes 9 and 10, the operation that introduces the new PSW is
completed, but an interruption occurs immediately
thereafter.
When the instruction address is odd (cause 1), the
instruction-length code (lLC) is 1,2, or 3, indicating
the number of halfword locations by which the in­
struction address has been incremented. It is unpre­
dictable whether the code is 1, 2, or 3.
For causes 2-8, the ILC is 1,2, or 3, designating
the length of the instruction causing the reference.
When the exception is recognized because of
causes 9 and 10 and the invalid bit value has been
introduced by LOAD PSW or an interruption, the
ILC is O. When the exception due to cause 10 is
Action On Exception
Protection
Exception
Addressing
Exception Explanation: DAT Table Entry Fetch
Suppress
Not applicable. I nstruction Fetch
Suppress
Suppress
Operand Reference
Terminate
1
, but suppress LPSW, SSM, STNSM, STOSM, SCKC, SPT, SPX
Terminate
1
, but suppress LPSW, SSM, STNSM, STOSM, SCKC, SPT, SPX
1 For termination, changes may occur only to result fields. I n this context, "result field" includes condition code, registers,
and storage locations, if any, which are designated to be changed by the instruction. However, no change is made to a
storage location or a key in storage when the reference causes an access exception. Therefore, if an instruction is due to
change only the contents of a field in main storage, and every byte of that field would cause an access exception, the
operation is suppressed.
Summary of Action for Protection and Addressing Exceptions
Interruptions 77