parallel or in series; the width of the arithmetic unit,
the multiplicity of the shifting paths, and the degree
of simultaneity in performing the different types of
arithmetic differ from one CPU to another without af­
fecting the logical appearance of the design.
Arithmetic and logical operations performed by the CPU fall into four classes: fixed-point arithmetic, deci­
mal arithmetic, floating-point arithmetic, and logical
operations. These classes differ in the data formats
used, the registers involved, the operations provided,
and the way the field length is stated.
Fixed-Point Arithmetic
The basic arithmetic operand is the 32-bit fixed-point
binary word. Sixteen-bit halfword operands may be
specified in most operations for improved performancc
or storage utilization. See Figure 6. To preserve
precision, some products and all dividends are 64 bits
o 1 15
o 1 31
Figure 6. Fixed-Point Number Formats
Because the 32-bit word size conveniently accom­
modates a 24-bit address, fixed-point arithmetic can
be used both for integer operand arithmetic and for
address arithmetic. This combined usage provides
economy and permits the entire fixed-point instruction
set and several logical operations to be used in ad­
dress computation. Thus, multiplication, shifting, and
logical manipulation of address components are pos­
The absence of recomplementation and the ease of
extension and truncation make two's-complement no­
tation desirable for address components and fixed­ point operands. Since integer and addressing algorisms
often require repeated reference to operands or inter­
mediate results, the use of multiple registers is advan­
tageous in arithmetic sequences and address calcula­
Additions, subtractions, multiplications, divisions,
and comparisons are performed upon one operand in
a register and another operand either in a register or
from storage. Multiple-precision operation is made
convenient by the two's-complement notation and by
recognition of the carry from one word to another. A
word in one register or a double word in a pair of
adjacent registers may be shifted left or right. A pair
of conversion instructions - CONVERT TO BINARY and CONVERT TO DECIMAL -provides transition between
decimal and binary radix (number base) without the
use of tables. Multiple-register loading and storing in­
structions facilitate subroutine switching. Decimal Arithmetic
Decimal arithmetic is designed for processes requiring
few computational steps between the source input
and the documented output. This type of processing
is frequently found in commercial applications, par­
ticularly when use is made of problem-oriented lan­
guages. Because of the limited number of arithmetic
operations performed on each item of data, radix con­
version from decimal to binary and back to decimal
is not justified, and the use of registers for intermedi­
ate results yields no advantage over storage-to-storage
processing. Hence, decimal arithmetic is provided,
and both operands and results are located in storage.
Decimal arithmetic includes addition, subtraction,
multiplication, division, and comparison.
Decimal numbers are treated as signed integers with
a variable-field-length format from one to 16" bytes
long. Negative numbers are carried in true form.
The decimal digits 0-9 are represented in the four­
bit binary-cod ed-decimal form by 0000-1001, respec­
tively. The codes 1010-1111 are not valid as digits and
are reserved for sign codes; 1011 and 1101 represent
a minus; the other four codes are interpreted as plus.
The sign codes generated in decimal arithmetic de­
pend upon the character set preferred (Figure 7).
When the expanded binary coded decimal interchange
code (EBCDIC) is preferred, the codes are 1100 and 1101. When the ASCII set, expanded to eight bits, is
preferred, the codes are 1010 and 1011. The choice
between the two code sets is determined by a mode
Decimal operands are represented by four-bit bin­
ary-coded-decimal digits packed two to a byte. They
appear in fields of variable length and are accompa­
nied by a sign in the rightmost four bits of the low-
Digit Code Sign Code 0 0000 + 1010 1 0001 - 1011 2 0010 + 1100 3 0011 - 1101 4 0100 + 1110 5 0101 + 1111
6 0110 7 0111 8 1000 9 1001 Pigure 7. Bit Codes for Digits and Signs
order byte. Operand fields may be located on any
byte boundary, and may have length up to 31 digits
and sign. Operands participating in an operation have
independent lengths. Packing of digits within a byte
(Figure 8) and of variable-length fields within stor­ age results in efficient use of storage, in increased
arithmetic performance, and in an improved rate of
data transmission between storage and files. I Digit I Digit I Digit Digit I Digit I Digit I Digit I Sign I I Zone I Digit I Zone C-_- Digit I Zone I Digit I Sign I Digit I Figure 8. Packed and Zoned Decimal Number Formats
Decimal numbers may also appear in a zoned for­ mat as a subset of the eight-bit alphameric character
set (Figure 8). This representation is required for
character-set sensitive I/O devices. The zoned format
is not used in decimal arithmetic operations. Instruc­ tions are provided for packing and unpacking decimal
numbers so that they may be changed from the zoned
to the packed format and vice versa.
Floating-Point Arithmetic
Floating-point numbers occur in either of two fixed­ length formats -short or long. These formats differ
only in the length of the fractions (Figure 9).
Short Floating-Point Number IS I Characteristic I Fraction
o I 7 8 31
Long Floating-Point Number _________ F_ra_c_ti_o_n ______ ______ o 1 78 63
Figure 9. Short and Long Floating-Point Number Formats Operands are either 32 or 64 bits long. The short
length, equivalent to seven decimal places of pre­ cision, permits a maximum number of operands to be
placed in storage and gives the shortest execution
times. The long length, used when higher precision is
desired, gives up to 17 decimal places of precision,
thus eliminating most requirements for double-pre­ cision arithmetic.
The operand lengths, being powers of two, permit
maximum efficiency in the use of binary addressing
and in matching the phys,ical word sizes of storage.
Floating-point arithmetic is designed to allow easy
transition between the two formats.
The fraction of a floating-point number is expressed
in hexadecimal ( base 16) digits, each consisting of
four binary bits and having the values 0-15. In the
short format, the fraction consists of six hexadecimal
digits occupying bits 8-31. In the long format the
fraction has 14 hexadecimal digits occupying bits 8-63.
The radix point of the fraction is assumed to be im­ mediately to the left of the high-order fraction digit.
To provide the proper magnitude for the floating­ point number, the fraction is considered to be mul­ tiplied by a power of 16. The characteristic portion,
bits 1-7 of both formats, is used to indicate this power.
The characteristic is treated as an excess 64 number
with a range from -64 through +63, and permits
representation of decimal numbers with magnitudes
in the range of 10-
to 10
Bit position 0 in either format is the sign (S) of the
fraction. The fraction of negative numbers is carried
in true form.
Four 64-bit floating-point registers are provided.
Arithmetic operations are performed with one oper­ and in a register and another either in a .register or
from storage. The result, developed in a register, is
generally of the same length as the operands. The
availability of several floating-point registers elimi­ nates much storing and loading of intermediate re­ sults. Logical Operations
Logical information is handled as fixed-length and
variable-length data. It is subject to such operations as
comparison, translation, editing, bit testing, and bit
When used as a fixed-length operand, logical in­ formation can consist of either one, four, or eight
bytes and is processed in the general registers.
A large portion of logical information consists of
alphabetic or numeric character codes, called alpha­ meric data, and is used for communication with char­ acter-set sensitive I/O devices. This information has
the variable-field-Iength format and can consist of up
to 256 bytes (Figure 10). It is processed in storage,
left to right, an eight-bit byte at a time.
The CPU can handle any eight-bit character set, al­ though certain restrictions are assumed in the decimal
arithmetic and editing operations. However, all char­ acter-set sensitive I/O equipment will assume either
the extended binary-coded-decimal interchange code
System Structure 11
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