L- ____ F_ir_s.t __ ______ -; ____ s_ec_o_n_d __ ________ r Byte' Byte 2 I :0 1 I I I 10 I I Register Register Operand' Operand 2 Op Code I R 1 I R2 I RR Format
7 8 11 12 15 1 Register Operand' Op Code I R, I X, B2
7 8 11 12 1516 I I I Register Register Operand' Operand 3 r---' ..---A-----y 7 8 I 11 12 Immediate Op Code 12 1516 I 78 1516 I 1 I I 1920 1920 1920 Address Operand 2 " D2
Address ___ _
Address Oper?nd 1
31 1 I I RX Format
RS Format SI Format I Length I Address Address ____ __ SS Format Op Code I L, I L2 I B, D,
7 8 11 12 15 16 1920 ------.-31-'--------1----------------'47 Figure 13. Five Basic Instruction Formats
struction stream in main storage, and operands lo­
cated in the general or floating-point registers.
To permit the ready relocation of program seg­
ments and to provide for the flexible specifications of
input, output, and working areas, all instructions re­
ferring to main storage have been given the capacity
of employing a full address.
The address used to refer to main storage is gen­
erated from the following three binary numbers:
Base Address (B) is a 24-bit number contained in a
general register specified by the program in the B
field of the instruction. The B field is included in
every address specification. The base address can be
used as a means of static relocation of programs and
data. In array-type calculations, it can specify the lo­
cation of an array and, in record-type processing, it
can identify the record. The base address provides for
addressing the entire main storage. The base address
may also be used for indexing purposes.
Index (X) is a 24-bit number contained in a general
register specified by the program in the X field of the
instruction. It is included only in the address speci-
fied by the RX instruction format. The index can be
used to provide the address of an element within an
array. Thus, the RX format instructions permit double
Displacement (D) is a 12-bit number contained in
the instruction format. It is included in every address
computation. The displacement provides for relative
addressing up to 4095 bytes beyond the element or
base address. In array-type calculations the displace­
ment can be used to specify one of many items as­
sociated with an element. In the processing of records,
the displacement can be used to identify items within
a record.
In forming the address, the base address and index
are treated as unsigned 24-bit positive binary integers.
The displacement is similarly treated as a 12-bit posi­
tive binary integer. The three are added as 24-bit
binary numbers, ignoring overflow. Since every ad­
dress includes a base, the sum is always 24 bits long.
The address bits are numbered 8-31 corresponding to
the numbering of the base address and index bits in
the general register.
The program may have zeros in the base address,
index, or displacement fields. A zero is used to indi­
cate the absence of the corresponding address com­
ponent. A base or index of zero implies that a zero
quantity is to be used in forming the address, regard­
less of the contents of general register O. A displace­
ment of zero has no special significance. Initialization,
modification, and testing of base addresses and in­
dexes can be carried out by fixed-point instructions,
As an aid in describing the logic of the instruction
format, examples of two instructions and their related
instruction formats follow. RR Format I Add 7 9
o 78 1112 15
Execution of the ADD instruction adds the contents of
general register 9 to the contents of general register
7 and the sum of the addition is placed in general
register 7.
RX Format
Store 3 10 14 300 7 8 11 1 2 15 16 1 9 20 31
Execution of the STORE instruction stores the contents
of general register 3 at a main-storage location ad­
dressed by the sum of 300 and the low-order 24 bits
of general registers 14 and 10. Sequential Instruction Execution
Normally, the operation of the CPU is controlled by
instructions taken in sequence. An instruction is
fetched from a location specified by the current in­
struction address. The instruction address is then in­
creased by the number of bytes in the instruction to
address the next instruction in sequence. The instruc­
tion is then executed and the same steps are repeated
using the new value of the instruction address.
Conceptually, all halfwords of an instruction are
fetched from storage after the preceding operation is
completed and before execution of the current oper­
ation, even though physical storage word size and
overlap of instruction execution with storage access
may cause actual instruction fetching to be different.
Thus, it is possible to modify an instruction in storage
by the immediately preceding instruction.
A change from sequential operation may be caused
by branching, status switching, interruptions, or man­
ual intervention.
The normal sequence of instructions is changed when
reference is made to a subroutine, when a two-way
choice is encountered, or when a segment of coding,
such as a loop, is to be repeated. All these tasks can
be accomplished with branching instructions.
Subroutine linkage permits not only the intro­
duction of a new instruction address but also the pres­
ervation of the return address and associated informa­
Decision-making is generally and symmetrically
provided by the BRANCH ON CONDITION instruction.
This instruction inspects a two-bit condition code that
reflects the result of a majority of the arithmetic, logi­
cal, and I/O operations. Each of these operations can
set the code in anyone of four states, and the con­
ditional branch can specify any selection of these four
states as the criterion for branching. For example, the
condition code reflects such conditions as nonzero,
first operand high, equal, overflow, channel busy, zero,
etc. Once set, the condition code remains unchanged
until modified by an instruction that reflects a dif­
ferent condition code.
The two bits of the condition code provide for four
possible condition code settings: 0, 1, 2, and 3. The
specific meaning of any setting is significant only to
the operation setting the condition code.
Loop control can be performed by the conditional
branch when it tests the outcome of address arith­
metic and counting operations. For some particularly
frequent combinations of arithmetic and tests, the in­
provided. These branches, being specialized, provide
increased performance for these tasks.
Program Status Word
A double word, the program status word (psw), con­
tains the information required for proper program
execution. The psw includes the instruction address,
condition code, and other fields to be discussed. In
general, the psw is used to control instruction se­
quencing and to hold and indicate the status of the
system in relation to the program being executed. The
active or controlling psw is called the "current psw." By storing the current psw during an interruption, the
status of the CPU can be preserved for subsequent in­
spection. By loading a new psw or part of a psw, the
state of the CPU can be initialized or changed. Figure
14 shows the psw format.
System Structure 15
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