operation code, but is stated explicitly, the informa­
tion is said to have variable field length. Variable­
length operands are variable in length by increments
of one byte.
Within any program format or any fixed-length op­
erand format, the bits making up the format are con­
secutively numbered from left to right starting with
the number O. Byte Halfword 11 0 0 1 Jo 0 0 1 11 0 1 0 KO 0 1 01 15
Word 11 0 0 011 0 0 111 0 0 0 BO 0 1 011 0 0 1'1> 1 0 011 1 1 0 1 11 16 24 31
Figure 2. Sample Information Formats
Byte locations in storage are consecutively numbered
starting with 0; each number is considered the ad­
dress of the corresponding byte. A group of bytes in
storage is addressed by the leftmost byte of the group.
The addressing capability permits a maximum of
16,777,216 bytes, using a 24-bit binary address. This
set of main-storage addresses includes some locations
reserved for special purposes.
Storage addressing wraps around from the maximum
byte address, 16,777,215, to address O. Variable-length
operands may be located partially in the last and par­
tially in the first location of storage, and are processed
without any special indication.
When only a part of the maximum storage capacity
is available in a given installation, the available stor­
age is normally contiguously addressable, starting at
address O. An addressing exception is recognized
when any part of an operand is located beyond the
maximum available capacity of an installation.
In some models main storage may be shared by
more than one CPU. In that case, the address of a byte
location is normally the same for each CPU. Informatic)n Positioning Fixed-length fields, such as halfwords and double
words, must be located in main storage on an integral
boundary for that unit of information. A boundary is
called integral for a unit of information when its stor-
age address is a multiple of the length of the unit in
bytes. For example, words (four bytes) must be lo­
cated in storage so that their address is a multiple of
the number 4. A halfword (two bytes) must have an
address that is a multiple of the number 2, and double
words (eight bytes) must have an address that is a
multiple of the number 8.
Storage addresses are expressed in binary form. In
binary, integral boundaries for halfwords, words, and
double words can be specified only by the binary ad­
dresses in which one, two, or three of the low-order
bits, respectively, are zero. (Figure 3). For example,
the integral boundary for a word is a binary address
in which the two low-order positions are zero.
Varia ble fields are not limited to integral bounda­
ries' but may start on any byte location.
Binary 0000 0001 0010 0011 0100 01Ql 0110 0111 1000 1001 1010 Address
Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte Byte
Halfword Halfword Halfword Halfword Halfword , l Word Word Word -( Double-Word Double-Word
Figure 3. Integral Boundaries for Halfwords, Words, and
Central Processing Unit ) l
The central processing unit (Figure 4) contains the
facilities for addressing main storage, for fetching or
storing information, for arithmetic and logical proc­
essing of data, for sequencing instructions in the de­
sired order, and for initiating the communication be­
tween storage and external devices.
The system control section provides the normal CPU control that guides the CPU through the operation
necessary to execute the instructions. While the
physical make-up of the control section in the various
models of the Systems/360 may be different, the
logical function remains the same.
The CPU provides 16 general registers for fixed-point
operands and four floating-point registers for floating­
point operands. Implementation of these registers may
be in active elements, in a local storage unit, or in a
separate area of main storage. In each case, the ad­
dress and functions of these registers are identical. , l
Storage Address
r- -'- -lOll( I I Instructions I Co mputer I I Sys tem I I Co ntrol , ..... Indexed Address I I I I I I L_
__ .-J Fixed Point
Operations MAIN STORAGE Variable Field Length
Operations J Floating Point
16 General Registers I Floating Point Registers
Figure 4. Central Processing Unit General Registers
The CPU can address information in 16 general regis­
ters. The general registers can be used as index regis­
ters, in address arithmetic and indexing, and as ac­
cumulators in fixed-point arithmetic and logical oper­ ations. The registers have a capacity of one word (32
bits). The general registers are identified by numbers 0-15 and are selected by a four-bit field in the in­ struction called the R field (Figure 5).
R Field Reg No. General Registers Floating Point Registers 0000 0 !i±32 Bits. hi:"":.'::::"': 64 Bits :::':":::::::::::::::;1I!l:1 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6
....... ,,' .. ··· .. ·'·:1 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14
1111 15
Figure 5. General and Floating-Point Registers
For some operations, two adjacent registers can be
coupled together, providing a two-word capacity.
In these operations, the addressed register contains
the high-order operand bits and must have an even
address, while the implied register, containing the
low-order operand bits, has the next higher address. Floating-Point Registers
Four floating-point registers are available for floating­ point operations. These registers are two words (64
bits) in length and can contain either a short (one
word) or a long (two word) floating-point operand.
A short operand occupies the high-order bits of a
floating-point register. The low-order portion of the
register is ignored and remains unchanged in short­ precision arithmetic. The floating-point registers are
identified by the numbers 0, 2, 4, and 6 (Figure 5).
The operation code determines which type of register
is to be used in an operation.
Arithmetic and Logical Unit
The arithmetic and logical unit can process binary in­
tegers and floating-point fractions of fixed length, deci­ mal integers of variable length, and logical information
of either fixed or variable length. Processing may be in System Structure 9
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