Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3
Program Interruptions: None.
Programming Note
When the same register is specified as first and second
operand location, the operation is equivalent to a test
without data movement.
Load Complement LCR RR. 13
78 1112 15
The two's complement of the second operand is placed
in the first operand location.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program in­
terruption when the fixed-point overflow mask bit is
one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Interruptions:
Fixed-point overflow Programming Note Zero rema.ins invariant under complementation.
Load Posit'ive LPR RR 10 78 1112 15
The absolute value of the second operand is placed in
the first operand location.
The operation includes complementation of nega­
tive numbers; positive numbers remain unchanged.
An overflow condition occurs when the maximum
negative number is complemented; the number re­
mains unchanged. The overflow causes a program in­
terruption when the fixed-point overflow mask bit is
one.
26
Resulting Condition Code:
o Result is zero
1
2 Result is greater than zero
3 Overflow Program Interruptions:
Fixed-point overflow Load Negative
LNR RR
11
78 1112 15
The two's complement of the absolute value of the
second operand is placed in the first operand location.
The operation complements positive numbers; nega­
tive numbers remain unchanged. The number zero
remains unchanged with positive sign.
Resulting Condition Code:
o Result is zero
1 Rcsult is less than zero
2
3
Program Inten'uptions: None.
Load Multiple
LM RS 98
7 8 11 1 2 15 16 1 9 20 31
The set of general registers starting with the register
specified by RI and ending with the register specified
by Ra is loaded from the locations designated by the
second opcrand address.
The storage area from which the contents of the
general registers are obtained starts at the location
designated by the second operand address and con­
tinues through as many words as needed. The general
registers are loaded in the ascending order of their
addresses, starting with the register specified by RI and continuing up to and including the register speci­
fied by R a , with register 0 following register 15.
The second operand remains unchanged.
Condition Code: The code remains unchanged.
Program Interruptions:
Addressing
Specification

Programming Note
All combinations of register addresses specified by Rl
and Ra are valid. When the register addresses are
equal, only one word is transmitted. When the address
specified by Ra is less than the address specified by R
1
,
the register addresses wrap around from 15 to O. Add
AR RR
lA
7 8 11 12 15
A
RX
5A
7 8 11 12 15 16 1920 31
The second operand is added to the first operand,
and the sum is placed in the first operand location.
Addition is performed by adding all 32 bits of both
operands. If the carries out of the sign-bit position and
the high-order numeric bit position agree, the sum is
satisfactory; if they disagree, an overflow occurs. The
sign bit is not changed after the overflow. A positive
overflow yields a negative final sum, and a negative
overflow results in a positive sum. The overflow causes
a program interruption when the fixed-point overflow
mask bit is one.
Resulting Condition Code:
o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow Program Interruptions:
Addressing (A only)
Specification (A only)
Fixed-point overflow
Programming Note
In two's-complement notation, a zero result is always
positive.
Add Halfword AH RX
4A
7 8 11 12 15 16 1920 31
The halfword second operand is added to the first
operand and the sum is placed in the first operand
location.
The halfword second operand is expanded to a full-
word before the addition by propagating the sign-bit
value through the 16 high-order bit positions.
Addition is performed by adding all 32 bits of both
operands. If the carries out of the sign-bit position
and the high-order numeric bit position agree, the
sum is satisfactory; if they disagree, an overflow oc­
curs. The sign bit is not changed after the overflow.
A positive overflow yields a negative final sum, and a
negative overflow results in a positive sum. The over­
flow causes a program interruption when the fixed­
point overflow mask bit is one.
Resulting Condition Code:
o Sum is zero
1 Sum is less than zero
2 Sum is greater than zero
3 Overflow Program Interruptions:
Addressing
Specification
Fixed-point overflow
Add Logical ALR RR
1 E
78 11 12 15
AL RX
5E
78 1112 1516 1920 31
The second operand is added to the first operand, and
the sum is placed in the first operand location. The oc­
currence of a carry out of the sign position is recorded
in the condition code.
Logical addition is performed by adding all 32 bits
of both operands without further change to the result­
ing sign bit. The instruction differs from ADD in the
meaning of the condition code and in the absence of
the interruption for overflow.
If a carry out of the sign position occurs, the leftmost
bit of the condition code (psw bit 34) is made one. In
the absence of a carry, bit 34 is made zero. When the
sum is zero, the rightmost bit of the condition code
(psw bit 35) is made zero. A nonzero sum is indicated
by a one in bit 35.
Resulting Condition Code:
o Sum is zero (no carry)
1 Sum is not zero (no carry)
2 Sum is zero (carry)
3 Sum is not zero (carry)
Fixed-Point Arithmetic 27