is the instruction-length code (2) of

ponents from which an address is generated -the

content of the Dl field and the content of the register

specified by

An unavailable or odd branch address of a successful

branch

instruction and not as part of the branch.

CONDITION

Fixed-Point Arithmetic

Add H/F zero

Add Logical zero

Compare H/F

Load and Test

Load Complement

Load Negative

Load Positive

Subtract Logical

Decimal Arithmetic

Add Decimal

Compare Decimal

Subtract Decimal

Zero and Add

equal

zero

zero

zero

zero

zero

zero

zero

zero

zero

zero

equal

zero

zero

Floating-Point Arithmetic

Add Normalized

Add Unnormalized

Compare

Load and Test

Load Complement

Load Negative

Load Positive

Subtract Normal-

ized

Subtract Unnorm-

alized

66

1

< zero

not zero

low

< zero

< zero

< zero

< zero

< zero

< zero

< zero

< zero

not zero

< zero

low

< zero

< zero

< zero

< zero

low

< zero

< zero

< zero

< zero

< zero

2

> zero

zero,

carry

high

> zero

> zero

> zero

> zero

> zero

> zero

> zero

> zero

carry

zero,

carry

> zero

high

> zero

> zero

> zero

> zero

high

> zero

> zero

> zero

> zero

> zero

3

overflow

carry

carry

overflow

overflow

overflow

overflow

overflow

carry

overflow

overflow

overflow

overflow

overflow

overflow

overflow

Logical Operations

And zero

equal

zero

zero

zero

zero

zero

zero

not zero

Compare Logical

Edit

Edit and Mark

Exclusive

Translate and Test

low

< zero

< zero

not zero

not zero

mixed

high

> zero

> zero

incomplete complete

one

I nput-Output Operations

Halt

Test

busy

carry

complete

equal

F

> zero

H

halted

high

incomplete

L

< zero

low

mixed

not oper

not working

not zero

one

overflow

working

zero

not

working

available

not

working

available

halted

stopped not oper

busy not oper

working not oper

working not oper

A carryout of the sign position occurs

Last result byte nonzero

Channel status word ready for test or

interruption

Chanel status word stored

Operands compare equal

Fullword

Result is greater than zero

Halfword

Data transmission stopped.

mode

First operand compares high

Nonzero result byte; not last

Long precision

Result is less than zero

First operand compares low

Selected bits are both zero and one

Result is not all zero

Selected bits are one

Result overflows

Data transmission stopped

Result or selected bits are zero

interrupti on.