PSW is the address of the instruction following EXECUTE. Similarly, the instruction-length code in the old psw
is the instruction-length code (2) of EXECUTE. The address restrictions do not apply to the com­
ponents from which an address is generated -the
content of the Dl field and the content of the register
specified by B 1 Programming Note
An unavailable or odd branch address of a successful
branch is detected during the execution of the next
instruction and not as part of the branch.
CONDITION CODE SETTING o
Fixed-Point Arithmetic
Add H/F zero
Add Logical zero
Compare H/F
Load and Test
Load Complement
Load Negative
Load Positive Shift Left Double Shift Left Single Shift Right Double Shift Right Single Subtract H/F
Subtract Logical
Decimal Arithmetic
Add Decimal
Compare Decimal
Subtract Decimal
Zero and Add
equal
zero
zero
zero
zero
zero
zero
zero
zero
zero
zero
equal
zero
zero
Floating-Point Arithmetic
Add Normalized S/L zero
Add Unnormalized S/L zero
Compare S/L equal
Load and Test S/L zero
Load Complement S/L zero
Load Negative S/L zero
Load Positive S/L zero
Subtract Normal-
ized S IL zero
Subtract Unnorm-
alized S/L zero
66
1
< zero
not zero
low
< zero
< zero
< zero
< zero
< zero
< zero
< zero
< zero
not zero
< zero
low
< zero
< zero
< zero
< zero
low
< zero
< zero
< zero
< zero
< zero
2
> zero
zero,
carry
high
> zero
> zero
> zero
> zero
> zero
> zero
> zero
> zero
carry
zero,
carry
> zero
high
> zero
> zero
> zero
> zero
high
> zero
> zero
> zero
> zero
> zero
3
overflow
carry
carry
overflow
overflow
overflow
overflow
overflow
carry
overflow
overflow
overflow
overflow
overflow
overflow
overflow
Logical Operations
And zero
equal
zero
zero
zero
zero
zero
zero
not zero
Compare Logical
Edit
Edit and Mark
Exclusive Or Or Test Under Mask
Translate and Test
low
< zero
< zero
not zero
not zero
mixed
high
> zero
> zero
incomplete complete
one
I nput-Output Operations
Halt I/O Start I/O Test Channel
Test I/O NOTES available
busy
carry
complete CSW ready CSW stored
equal
F
> zero
H
halted
high
incomplete
L
< zero
low
mixed
not oper
not working
not zero
one
overflow S stopped
working
zero
not
working
available
not
working
available
halted CSW stored CSW ready CSW stored
stopped not oper
busy not oper
working not oper
working not oper Unit and channel available Unit or channel busy
A carryout of the sign position occurs
Last result byte nonzero
Channel status word ready for test or
interruption
Chanel status word stored
Operands compare equal
Fullword
Result is greater than zero
Halfword
Data transmission stopped. Unit in halt-reset
mode
First operand compares high
Nonzero result byte; not last
Long precision
Result is less than zero
First operand compares low
Selected bits are both zero and one Unit or channel not operational Unit or channel not working
Result is not all zero
Selected bits are one
Result overflows Short precision
Data transmission stopped U nit or channel working
Result or selected bits are zero NOTE: The condition code also may be changed by LOAD PSW, SET SYSTEM MASK, and DIAGNOSE and by an
interrupti on.
A set of operations is provided to switch the status of
the CPU, of storage, and of communication between
systems.
The over-all CPU status is determined by several
program-state alternatives, each of which can be
changed independently to its opposite and most of
which are indicated by a bit in the program status
word (psw). The CPU status is further defined by the
instruction address, the condition code, the instruction­
length code, the storage-protection key, and the inter­
ruption code. These all occupy fields in the psw.
Storage is protected by storage keys, which are
matched with a protection key in the psw or in a chan­
nel. The protcction status of storage may be changed
by introducing new storage keys, using SET STORAGE KEY. The storage keys may be inspected by using IN­ SERT STORAGE KEY.
The system formed by CPU, storage, and I/O can
communicate with other systems by means of the sig­
nals of the direct control feature and the multisystem
feature. The READ DIRECT makes signals available to
the CPU; WRITE DIRECT provides signals to other
systems.
All status-switching instructions, other than those of
the protection feature or direct control feature, are
provided in the standard instruction set.
Program States
The four types of program-state alternatives, which
determine the over-all CPU status, are named Problem/
Supervisor, Wait/Running, Masked/Interruptable, and
Stopped/Operating. These states differ in the way they
affect the CPU functions and in the way their status is
indicated and switched. Each state, except masked,
has one alternative.
All program states are independent of each other in
their function, indication, and status-switching. Status­
switching does not affect the contents of the arith­
metic registers or the execution of I/O operations but
may affect the timer operation. Problem State
The choice between supervisor and problem state de­
termines whether the full set of instructions is valid.
The names of these states reflect their normal use.
In the problem state all I/O, protection, and direct-
Status-Switch i ng
control instructions are invalid, as well as LOAD psw, SET SYSTEM MASK, and DIAGNOSE. These are called privi­
leged instructions. A privileged instruction encount­
ered in the problem state constitutes a privileged-op­
eration exception and causes a program interruption.
In the supervisor state all instructions are valid.
When bit 15 of the psw is zero, the CPU is in the
supervisor state. When bit 15 is one, the CPU is in the
problem state. The supervisor state is not indicated on
the operator sections of the system control panel.
The CPU is switched between problem and super­
visor state by changing bit 15 of the psw. This bit can
be changed only by introducing a new psw. Thus
status-switching may be performed by LOAD psw, using
a new psw with the desired value for bit 15. Since LOAD PSW is a privileged instruction, the CPU must be
in the supervisor state prior to the switch. A new psw
is also introduced when the CPU is interrupted. The SUPERVISOR CALL causes an interruption and thus may
change the CPU state. Similarly, initial program load­
ing introduces a new psw and with it a new CPU state.
The new psw may introduce the problem or supervisor
state regardless of the preceding state. No explicit op­
erator control is provided for changing the supervisor
state.
Timer updating is not affected by the choice be­
tween supervisor and problem state.
Programming Note
To allow return from an interruption-handling routine
to a preceding program by a LOAD psw, the psw for
the interruption routine should specify the supervisor
state.
Wait State
In the wait state no instructions are processed, and
storage is not addressed repeatedly for this purpose,
whereas in the running state, instruction fetching and
execution proceed in the normal manner.
When bit 14 of the PSW, is one, the CPU is waiting.
When bit 14 is zero, the CPU is in the running state.
The wait state is indicated on the operator control
section of the system control panel by the wait light.
The CPU is switched between wait and running state
by changing bit 14 of the psw. This bit can be changed
only by introducing an entire new PSW, as is the case
with the problem-state bit. Thus, switching from the Status Switching 67
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