Read Direct
RDD 51 85
78 15 16 1920 31
Eight instruction bits are made available as signal-out
timing signals. A direct-in data byte is accepted from
an external device in the absence of a hold signal and
is placed in the location designated by the operand
Instruction bits 8-15, the 12 field, are made available
on a set of eight signal-out lines as O.5-microsecond to
l.O-microsecond timing signals. These signal-out lines
are also used in WRITE DIRECT. On a ninth line (Read Out) a O.5-microsecond to l.O-microsecond timing
signal is made available coincident with these timing
signals. The read-out line is distinct from the write-out
line in WRITE DIRECT. No parity is made available with
the eight instruction bits.
Eight data bits are accepted from a set of eight
direct-in Hnes. when the hold signal on the hold-in
line is absent. The hold signal is sampled after the
read-out signal has been completed and should be
absent for at least O.5-microsecond. No parity is ac­
cepted with data signals, but a parity bit is generated
as the data are placed in storage. When the hold sig­
nal is not removed, the CPU does not complete the in­
struction. Excessive duration of this instruction may
result in incomplete updating of the timer.
Condition Code: The code remains unchanged. Program Interruptions: Operation (if direct control feature is not installed)
Privileged operation
Addressing Programming Note
The direct-out lines of one CPU may be connected to
the direct-in lines of another CPU, providing cpu-to-cpu
static signaling. Further, the write-out signal of the
sending CPU may serve as the hold signal for the re­
ceiving CPU, temporarily inhibiting a READ DIRECT when
the signals are in transition.
Equipment connected to the hold-in line should be
so constructed that the hold signal is removed when
READ DIRECT is performed. Absence of the hold signal
should correspond to absence of current in such a
fashion that the CPU can proceed when power is re­
moved from the source of the hold signal.
Diagnose 51 83
78 1516 1920 31
The CPU performs built-in diagnostic functions.
The purpose of the h field and the operand address
may be defined in greater detail for a particular CPU and its appropriate diagnostic procedures. Similarly,
the number of low-order address bits which must be
zero is further specified for a particular CPU. When the
address does not have the required number of low­
order zeros, a specification exception causes a program
The purpose of the diagnostic functions is verifica­
tion of proper functioning of the CPU equipment and
locating faulty components.
The DIAGNOSE is completed either by taking the next
sequential instruction or by obtaining a new psw from
location 112. The diagnostic procedure may affect the
problem, supervisor, and interruptable status of the CPU, the condition code, and the contents of storage,
registers, and timer, as well as the progress of 1/0 operations. Some diagnostic functions turn on the test light on
the operator control section of the system control
panel. Since the instruction is not intended for problem­
program or supervisor-program use, DIAGNOSE has no
Condition Code: The code is unpredictable. Program Interruptions:
Privileged operation
Status-Switching Exceptions
Exceptional instructions or data cause a program in­
terruption. When the interruption occurs, the current
psw is stored as an old PSW, and a new psw is obtained.
Thc interruption code inserted in the old psw identi­
fies the cause of the interruption. The following ex­
ception conditions cause a program interruption in
status-switching operations.
Operation: The direct control feature is not installed,
and the instruction is READ DIRECT or WRITE DIRECT; or,
the protection feature is not installed and the instruc­
READ DIRECT, or DIAGNOSE is encountered while the
processor is in the problem state.
Protection: The storage key of the location desig­
nated by READ DIRECT does not match the protection
key in the psw.
Addressing: An address designates a location out­
side the available storage for the installed model.
Specification: The operand address of a LOAD psw does not have all three low-order bits zero; the operand
address of DIAGNOSE does not have as many low-order
zero bits as required for the particular CPU; the
block address specified by SET STORAGE KEY or INSERT STORAGE KEY does not have the four low-order bits aII­
zero; or the protection feature is not installed and a
psw with two nonzero protection keys is introduced.
In most of the above interruption conditions, the in­
struction is suppressed. Therefore, storage and exter­
nal signals remain unchanged, and the psw is not
changed by information from storage. The only ex­
ception is READ DIRECT, which is terminated when a
protection or addressing violation is detected. Al­
though storage remains unchanged, a timing signal
may have been made available.
When an interruption is taken, the instruction ad­
dress stored as part of the old psw has been updated
by the number of halfwords indicated by the instruc­
tion-length code in the old psw. Operand addresses are tested only when used to ad­
dress storage. The address restrictions do not apply
to the components from which an address is generated:
the content of the Dl field and the content of the
register specified by B1. Status Switching 75
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