Shift Left Single SLA RS 8B

7 8 11 12 15161920 31

The integer part of the first operand is shifted left the

numberOIf bits specified by the second operand ad

dress.

The second operand address is not used to address

data; its low-order six bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The sign of the first operand remains unchanged. All

31 integer bits of the operand participate in the left

shift.Zeros are supplied to the vacated low-order reg

ister positions.

If a bit unlike the sign bit is shifted out of position

1, an overflow occurs. The overflow causes a program

interruption when the fixed-pointoverflow mask bit

is one.

Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3Overflow Program Interruptions: Fixed-point overflow.

Programming Note

The base register participating in the generation of the

second operand address permits indirect specification

of the shift amount. A zero in theB:! field indicates

the absence of indirect shift specification.

Shift Right Single

SRARS 8A

78]] 12 1516 1920 31

The integer part of the first operand is shifted right

the num her of bits specified by the second operand

address.

The second operand address is not used to address

data; its low-order six bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The sign of the first operand remains unchanged.

All 31 integer bits of the operand participate in the

right shift. Bits equal to the sign are supplied to the

vacated high-order bit positions. Low-order bits are

shifted out without inspection and are lost.

32

Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3Program Interruptions: None.

Programming Note

Right-shifting is similar to division by powers of two

and to low-order truncation.Since negative numbers

are kept in two's-complement notation, truncation is

in the negative direction for both positive and nega

tive numbers, rather than toward zero as in decimal

arithmetic.Shift amounts from 32 through 63 cause all signifi

cant digits to be shifted out of the register. They give

a zero result for positive numbers and a minus one

result for negative numbers.

Shift Left Double

SLDARS 8F

78]]/]2 1516 1920 31

The double-length integer part of the first operand is

shifted left the number of bits specified by the second

operand address.

The RL field of the instruction specifics an even/odd

pair of registers and must contain an even register

address. A specification exception occurs when Rl is

odd.

The second operand address is not used to address

data; its low-order 6-bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The operand is treated as a number with 63 integer

bits and a sign in the sign position of the even register.

The sign remains unchanged. The high-order position

of the odd register contains an integer bit, and the

content of the odd register participates in the shift inthe same manner as the other integer bits. Zeros are

supplied to the vacated low-order positions of the

registers.

If a bit unlike the sign bit is shifted out of bit posi

tion 1 of the even register, anoverflow occurs. The

overflow causes a program interruption when the fixed

point overflow mask bit is one.Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3Overflow

7 8 11 12 1516

The integer part of the first operand is shifted left the

number

dress.

The second operand address is not used to address

data; its low-order six bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The sign of the first operand remains unchanged. All

31 integer bits of the operand participate in the left

shift.

ister positions.

If a bit unlike the sign bit is shifted out of position

1, an overflow occurs. The overflow causes a program

interruption when the fixed-point

is one.

Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3

Programming Note

The base register participating in the generation of the

second operand address permits indirect specification

of the shift amount. A zero in the

the absence of indirect shift specification.

Shift Right Single

SRA

78

The integer part of the first operand is shifted right

the num her of bits specified by the second operand

address.

The second operand address is not used to address

data; its low-order six bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The sign of the first operand remains unchanged.

All 31 integer bits of the operand participate in the

right shift. Bits equal to the sign are supplied to the

vacated high-order bit positions. Low-order bits are

shifted out without inspection and are lost.

32

Resulting Condition Code:

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3

Programming Note

Right-shifting is similar to division by powers of two

and to low-order truncation.

are kept in two's-complement notation, truncation is

in the negative direction for both positive and nega

tive numbers, rather than toward zero as in decimal

arithmetic.

cant digits to be shifted out of the register. They give

a zero result for positive numbers and a minus one

result for negative numbers.

Shift Left Double

SLDA

78

The double-length integer part of the first operand is

shifted left the number of bits specified by the second

operand address.

The RL field of the instruction specifics an even/odd

pair of registers and must contain an even register

address. A specification exception occurs when Rl is

odd.

The second operand address is not used to address

data; its low-order 6-bits indicate the number of bit

positions to be shifted. The remainder of the address

is ignored.

The operand is treated as a number with 63 integer

bits and a sign in the sign position of the even register.

The sign remains unchanged. The high-order position

of the odd register contains an integer bit, and the

content of the odd register participates in the shift in

supplied to the vacated low-order positions of the

registers.

If a bit unlike the sign bit is shifted out of bit posi

tion 1 of the even register, an

overflow causes a program interruption when the fixed

point overflow mask bit is one.

o Result is zero

1 Result is less than zero

2 Result is greater than zero

3