Shift Left Single SLA RS 8B
7 8 11 12 1516 1920 31
The integer part of the first operand is shifted left the
number OIf bits specified by the second operand ad­
dress.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand remains unchanged. All
31 integer bits of the operand participate in the left
shift. Zeros are supplied to the vacated low-order reg­
ister positions.
If a bit unlike the sign bit is shifted out of position
1, an overflow occurs. The overflow causes a program
interruption when the fixed-point overflow mask bit
is one.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow Program Interruptions: Fixed-point overflow.
Programming Note
The base register participating in the generation of the
second operand address permits indirect specification
of the shift amount. A zero in the B:! field indicates
the absence of indirect shift specification.
Shift Right Single
SRA RS 8A
78 ]] 12 1516 1920 31
The integer part of the first operand is shifted right
the num her of bits specified by the second operand
address.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand remains unchanged.
All 31 integer bits of the operand participate in the
right shift. Bits equal to the sign are supplied to the
vacated high-order bit positions. Low-order bits are
shifted out without inspection and are lost.
32
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions: None.
Programming Note
Right-shifting is similar to division by powers of two
and to low-order truncation. Since negative numbers
are kept in two's-complement notation, truncation is
in the negative direction for both positive and nega­
tive numbers, rather than toward zero as in decimal
arithmetic. Shift amounts from 32 through 63 cause all signifi­
cant digits to be shifted out of the register. They give
a zero result for positive numbers and a minus one
result for negative numbers.
Shift Left Double
SLDA RS 8F
78 ]]/]2 1516 1920 31
The double-length integer part of the first operand is
shifted left the number of bits specified by the second
operand address.
The RL field of the instruction specifics an even/odd
pair of registers and must contain an even register
address. A specification exception occurs when Rl is
odd.
The second operand address is not used to address
data; its low-order 6-bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The operand is treated as a number with 63 integer
bits and a sign in the sign position of the even register.
The sign remains unchanged. The high-order position
of the odd register contains an integer bit, and the
content of the odd register participates in the shift in the same manner as the other integer bits. Zeros are
supplied to the vacated low-order positions of the
registers.
If a bit unlike the sign bit is shifted out of bit posi­
tion 1 of the even register, an overflow occurs. The
overflow causes a program interruption when the fixed­
point overflow mask bit is one. Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Overflow

Program Interruptions:
Specification
Fixed-point overflow
Shift Right Double SRDA RS 8E
78 1112 1516 1920 31
The double-length integer part of the first 9perand is
shifted right the number of places specified by the
second operand address.
The RI field of the instruction specifies an even/odd
pair of registers and must contain an even register
address. A specification exception occurs when RI is
odd.
The second operand address is not used to address
data; its low-order six bits indicate the number of bit
positions to be shifted. The remainder of the address
is ignored.
The sign of the first operand, which is leftmost in
the even register, remains unchanged. Bits equal to
the sign are supplied to the vacated high-order posi­
tions of both registers. Low-order bits are shifted out
without inspection and are lost.
Resulting Condition Code:
o Result is zero
1 Result is less than zero
2 Result is greater than zero
3 Program Interruptions:
Specification
Programming Note
A zero shift amount in the double-shift operations
provides a double-length sign and magnitude test.
fixed-Point Arithmetic Exceptions
Exceptional instructions, data, or results cause a pro­
gram interruption. When a program interruption oc­
curs, the current psw is stored as an old PSW, and a
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. The
following exceptions cause a program interruption in
fixed-point arithmetic.
Protection: The storage key of a result location does
not match the protection key in the psw. The opera­
tion is suppressed. Therefore, the condition code and
data in registers and storage remain unchanged. The
only exception is STORE MULTIPLE, which is terminated;
the amount of data stored is unpredictable and should
not be used for further computation.
Addressing: An address designates a location out­
side the available storage for a particular installation.
The operation is terminated. Therefore, the result data
are unpredictable and should not be used for further
computation. Operand addresses are tested only when
used to address storage. Addresses used as a shift
amount are not tested. The address restrictions do not
apply to the components from which an address is
generated -thc content of the D2 field and the con­
tents of the registers specified by X2 and B 2 • Specification: A double-word operand is not located
on a 64-bit boundary, a fuIlword operand is not located
on a 32-bit boundary, a halfword operand is not lo­
cated on a 16-bit boundary, or an instruction specifies
an odd register address for a pair of general registers
containing a 64-bit operand. The operation is sup­
pressed. Therefore, the condition code and data in reg­
isters and storage remain unchanged.
Data: A sign or a digit code of the decimal operand
in CONVERT TO BINARY is incorrect. The operation is
suppressed. Therefore, the condition code and data in
register and storage rcmain unchanged.
Fixed-Point Overflow: The result of a sign-control,
add, subtract, or shift operation overflows. The inter­
ruption occurs only when the fixed-point overflow
mask bit is one. The operation is completed by placing
the truncated low-order result in the register and set­
ting the condition code to 3. The overflow bits are lost.
In add-type operations the sign stored in the register
is the opposite of the sign of the sum or difference. In
shift operations the sign of the shifted number remains
unchanged. The state of the mask bit docs not affect
the result.
Fixed-Point Divide: The quotient of a division ex­
ceeds the register size, including division by zero, or
the result in CONVERT TO BINARY exceeds 31 bits. Divi­
sion is suppressed. Therefore, data in the registers
remain unchanged. The conversion is completed by re­
cording the truncated low-order result in the register. Fixed-Point Arithmetic 33