Multiply Halfword

MHRX 7 8 11 12 15 16 1920 31

The product of the halfword multiplier (second op

erand) and multiplicand (first operand) replaces the

multiplicand.

Both multiplicand and product are 32-bit signed

integers and may be located in any general register.

The half word multiplier is expanded to a fullword

before multiplication by propagating the sign-bit value

through the 16 high-order bit positions. The multi

plicand is replaced by the low-order part of the prod

uct. The bits to the left of the 32 low-order bits are

not tested for significance; no overflow indication is

given.

The sign of the product is determined by the rules

of algebra from the multiplier and multiplicand sign,

except that a zero result is always positive.

Condition Code: The code remains unchanged.Program Interruptions:

AddressingS pecifica tion

Programming Note

The significant part of the product usually occupies 46

bits or fewer, the exception being 47 bits when both

operands are maximum negative.Since the low-order

32 bits of the product are stored unchanged, ignoring

all bits to the left, the sign bit of the result may differ

from the true sign of the product in the case of over

flow.

Divide

DR RR

1D

7 8 11 12 15

D

RX

5D

7 8 11 1 2 15 16 1 920 31

The dividend (first operand) is divided by the divisor

(second operand) and replaced by the quotient and

remainder.

The dividend is a 64-bit signed integer and occupies

the even/odd pair of registers specified by the Rl field

of the instruction. A specification exception occurs30 when Rl is odd. A 32-bit signed remainder and a

32-bit signed quotient replace the dividend in the

even-numbered and odd-numbered registers, respec

tively. The divisor is a 32-bit signed integer.

The sign of the quotient is determined by the rules

of algebra. The remainder has the same sign as the

dividend, except that a zero quotient or a zero re

mainder is always positive. All operands and results

are treated as signed integers. When the relative

magnitude of dividend and divisor is such that the

quotient cannot be expressed by a 32-bit signed integ

er, a fixed-point divide exception is recognized (a

program interruption occurs, no division takes place,

and the dividend remains unchanged in the gcneral

registers) .

Condition Code: The code remains unchanged.Program Interruptions:

Addressing (D only)S pecifica tion

Fixed-point divide

Programming Note

Division applies to fullword operands in storage only ..Convert to Binary eva RX

4F

7 8 11 12 15 161920 31

The radix of the second operand is changed from deci

mal to binary, and the result is placed in the first

operand location. The number is treated as a right

aligned signed integer both before and after conver

sion.

The second operand has the packed decimal data

formatand is checked for valid sign and digit codes.

Improper codes are a data exception and cause a pro

gram interruption. The decimal operand occupies a

double-word storage field, which must be located on

an integral boundary. The low-order four bits of the

field represent the sign. The remaining60 bits contain

15 binary-coded-decimal digits in true notation. The

packed decimal data format is described under"Deci mal Arithmetic." The result of the conversion is placed in the general

register specified byR l • The maximum number that

can be converted and still be contained in a 32-bit

register is 2,147,483,647; the minimum number is

-2,147,483,648. For any decimal number outside this

range, the operation is completed by placing the 32

low-order binary bits in the register; a fixed-point

MH

The product of the halfword multiplier (second op

erand) and multiplicand (first operand) replaces the

multiplicand.

Both multiplicand and product are 32-bit signed

integers and may be located in any general register.

The half word multiplier is expanded to a fullword

before multiplication by propagating the sign-bit value

through the 16 high-order bit positions. The multi

plicand is replaced by the low-order part of the prod

uct. The bits to the left of the 32 low-order bits are

not tested for significance; no overflow indication is

given.

The sign of the product is determined by the rules

of algebra from the multiplier and multiplicand sign,

except that a zero result is always positive.

Condition Code: The code remains unchanged.

Addressing

Programming Note

The significant part of the product usually occupies 46

bits or fewer, the exception being 47 bits when both

operands are maximum negative.

32 bits of the product are stored unchanged, ignoring

all bits to the left, the sign bit of the result may differ

from the true sign of the product in the case of over

flow.

Divide

DR RR

1D

7 8 11 12 15

D

RX

5D

7 8 11 1 2 15 16 1 9

The dividend (first operand) is divided by the divisor

(second operand) and replaced by the quotient and

remainder.

The dividend is a 64-bit signed integer and occupies

the even/odd pair of registers specified by the Rl field

of the instruction. A specification exception occurs

32-bit signed quotient replace the dividend in the

even-numbered and odd-numbered registers, respec

tively. The divisor is a 32-bit signed integer.

The sign of the quotient is determined by the rules

of algebra. The remainder has the same sign as the

dividend, except that a zero quotient or a zero re

mainder is always positive. All operands and results

are treated as signed integers. When the relative

magnitude of dividend and divisor is such that the

quotient cannot be expressed by a 32-bit signed integ

er, a fixed-point divide exception is recognized (a

program interruption occurs, no division takes place,

and the dividend remains unchanged in the gcneral

registers) .

Condition Code: The code remains unchanged.

Addressing (D only)

Fixed-point divide

Programming Note

Division applies to fullword operands in storage only ..

4F

7 8 11 12 15 16

The radix of the second operand is changed from deci

mal to binary, and the result is placed in the first

operand location. The number is treated as a right

aligned signed integer both before and after conver

sion.

The second operand has the packed decimal data

format

Improper codes are a data exception and cause a pro

gram interruption. The decimal operand occupies a

double-word storage field, which must be located on

an integral boundary. The low-order four bits of the

field represent the sign. The remaining

15 binary-coded-decimal digits in true notation. The

packed decimal data format is described under

register specified by

can be converted and still be contained in a 32-bit

register is 2,147,483,647; the minimum number is

-2,147,483,648. For any decimal number outside this

range, the operation is completed by placing the 32

low-order binary bits in the register; a fixed-point