Interruption Action INSTRUC­ TION INTERRUPTION SOURCE IDENTIFICATION
INTERRUPTION CODE MASK ILC EXE- PSW BITS 16-31 BITS SET CUTION Input / Output ( old PSW 56, new PSW 120, priority 4)
Multiplexor channel 00000000 aaaaaaaa 0 x complete Selector channell 00000001 aaaaaaaa 1 x complete Selector channel 2 00000010 aaaaaaaa 2 x complete Selector channel 3 00000011 aaaaaaaa 3 x complete Selector channcl4 00000100 aaaaaaaa 4 x complete Selector channel 5 00000101 aaaaaaaa 5 x complete Selector channel 6 00000110 aaaaaaaa 6 x complete
Program ( old PSW 40, new PSW 104, priority 2) Operation 00000000 00000001 1,2,3 suppress Privileged operation 00000000 00000010 1,2 suppress
Execute 00000000 00000011 2 suppress Protection 00000000 00000100 0,2,3 suppress/
terminate
Addressing 00000000 00000101 1,2,3 suppress/
terminate Specification 00000000 00000110 1,2,3 suppress
Data 00000000 00000 III 2,3 terminate
Fixed-point overflow 0000000000001000 36 1,2 complete
Fixed-point divide 0000000000001001 1,2 suppress/
complete
Decimal overflow 00000000 00001 0 1 0 37 3 complete
Decimal divide 00000000 00001011 3 suppress
Exponent overflow 00000000 00001100 1,2 terminate
Exponent underflow 00000000 00001101 38 1,2 complete Significance 00000000 0000 III 0 39 1,2 complete
Floating-point divide 0000000000001111 1,2 suppress
Supervisol' Call ( old PSW 32, new PSW 96, priority 2)
Instruction bits 00000000 r r r r r r r r 1 complete
External ( old PSW 24, new PSW 88, priority 3 )
External signal 1 00000000 xxxxxxxi 7 x complete
External signal 2 00000000 xxxxxx1x 7 x complete
External signal 3 00000000 xxxxx1xx 7 x complete
External signal 4 00000000 xxxx1xxx 7 x complete
External signal 5 00000000 xxxlxxxx 7 x complete
External signal 6 00000000 xx1xxxxx 7 x complete
Interrupt key 00000000 xlxxxxxx 7 x complete
Timer 00000000 lxxxxxxx 7 x complete
Machine Check (old PSW 48, new PSW 112, priority 1)
Machine malfunction 00000000 00000000 13 x terminate NOTES a
r
x
Device address bits
Bits of Rl and R2 field of SUPERVISOR CALL
Unpredictable
Instruction Length Recording INSTRUC- TION INSTRUC- I,ENGTH PEW BITS TION INSTRUCTION CODE BITS 0-1 LENGTH 0 00 Not available
1 01 00 One halfword
2 10 01 Two halfwords
2 10 10 Two halfwords
3 11 11 Three halfwords
148 INSTRUC- TION FORMAT RR
RX RS or SI SS Program Interruptions
The listings in the "Type" and "Exceptions" columns
of the tables in this section mean:
A Addressing exception C Condition code is set
D Data exception
DF Decimal-overflow exception
DK Decimal-divide exception
E Exponent-overflow exception
EX Execute exception
F Floating-point feature
FK Floating-point divide exception
IF Fixed-point overflow exception
IK Fixed-point divide exception
L New condition code loaded LS Significance exception
M Privileged-operation exception
N Normalized operation P Protection exception S Specification exception
T Decimal feature U Exponent-underflow exception Y Direct control feature Z Protection feature
Operation (OP) The operation code is not assigned or the assigned
operation is not available on the particular cpu. The operation is suppressed.
The instruction-length code is 1, 2, or 3.
Privileged Operation (M)
A privileged instruction is encountered in the problem
state.
The operation is suppressed.
The instruction-length code is 1 or 2.
NAME MNEMONIC TYPE EXCEPTIONS CODE Diagnose SI M, A,S 83
Halt 110 IIIO SI C M, 9E
Insert Storage Key ISK RRZ M, A,S 09 Load PSW LPSW SI L M, A,S 82
Head Direct RDD SI Y M,P,A 85 Sct Storage Key SSK RRZ M, A,S 08 Set System Mask SSM SI C M, A 80 Start 110 SIO SI C M, 9C Test Channel TCH SI C M, 9F
Test 110 TIO SI C M, 9D
Writc Direct WRD SI Y M, A 84
Execute (EX)
The subject instruction of EXECUTE is another EXECUTE. The operation is suppressed.
The instruction-length code is 2.
NAME
Execute
Protection (P)
MNEMONIC
EX TYPE RX EXCEPTIONS CODE A,S, EX 44
The storage key of a result location does not match
the protection key in the psw.
The operation is suppressed, except in the case of
NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE STORE MULTIPLE, READ DIRECT, and variable-length op-
AND NI SI C P,A, 94 SPR erations, which are terminated.
AND NC SS C P,A D4 TRM
The instruction-length code is 0, 2, or 3. Compare C RX C A,S, 59 TRM Compare NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Decimal CP SS T,C A, D F9 TRM
Add Decimal AP SS T,C P,A, D, DF FA TRM Compare AND NI SI C P,A 94 SPR Halfword CH RX C A,S, 49 TRM
AND NC SS C P,A D4 TRM Compare Convert to
Logical CL RX C A,S, 55 TRM
Decimal CVD RX P,A,S 4E SPR Compare Divide Decimal DP SS T P,A,S,D, DK FD TRM
Logical CLI SI C A 95 TRM
Edit ED SS T,C P,A, D DE TRM Compare Edit: and Mark EDMK SS T,C P,A, D DF TRM
Logical CLC SS C A D5 TRM Exclusive OR XI SI C P,A 97 SPR Compare (Long) CD RXF,C A,S, 69 TRM
Exclusive OR XC SS C P,A D7 TRM Compare (Short) CE RXF,C A,S, 79 TRM
Move MVI SI P,A 92 SPR Convert to
Move MVC SS P,A D2 TRM
Binary CVB RX A,S,D, IK 4F TRM
Move Numerics MVN SS P,A D1 TRM Convert to
Move with
Decimal CVD RX P,A,S, 4E SPR Offset MVO SS P,A F1 TRM Diagnose SI M, A,S, 83 SPR Move Zones MVZ SS P,A D3 TRM Divide D RX A,S, IK 5D TRM
Multiply Divide Decimal DP SS T P,A,S,D, DK FO TRM
Decimal MP SS T P,A,S,D FC TRM Divide (Long) NDD RXF A,S,U,E,FK 60 TRM OR 01 SI C P,A 96 SPR Divide (Short) NDE RXF A,S,U,E,FK 70 THM OR OC SS C P,A D6 TRM Edit ED SS T,C P,A, D DE TRM Pack PACK SS P,A F2 TRM Edit and Mark EDMK SS T,C P,A, D DF TRM
Read Direct RDD SI Y M,P,A 85 TRM Exclusive OR X RX C A,S, 57 TRM Store ST RX P,A,S 50 SPR Exclusive OR XI SI C P,A, 97 SPR Store Character STC RX P,A 42 SPR Exclusive OR XC SS C P,A, D7 TRM Store Halfword STH RX P,A,S 40 SPR Execute EX RX A,S, EX 44 SPR Store Long STD RXF P,A,S 60 SPR Insert Character IC RX A 43 TRM Store Insert Storage
Multiple STM RXF P,A,S 90 TRM
Key ISK RRZ M, A,S 09 Store Short STE RXF P,A,S 70 SPR Subtract
Load L RX A,S, 58 TRM
Decimal SP SS T,C P,A, D, DF FB TRM
Load Halfword LH RX A,S, 48 TRM
Translate TR SS P,A DC TRM
Load (Long) LD RXF A,S, 68 TRM Unpack UNPK SS P,A F3 TRM
Load Multiple LM RS A,S, 98 TRM Zero and Add ZAP SS T,C P,A, D, DF F8 TRM
Load PSW LPSW SI LM, A,S 82 TRM
Load (Short) LE RXF A,S, 78 TRM PROTECTION INTERRUPTION NOTES Move MVI SI P,A 92 SPR SPR = Operation suppressed Move MVC SS P,A D2 TRM
TRM = Operation terminated Move Numerics MVN SS P,A D1 TRM
Addressing (A)
Move with Offset MVO SS P,A Fl TRM
Move Zones MVZ SS P,A D3 TRM
An address specifies any part of data, instructions, or Multiply M RX A,S 5C TRM
control words outside the available storage for the par-
Multiply
ticular installation.
Decimal MP SS T P,A,S,D FCTRM Multiply
The operation is terminated. Data in storage remain IIalfword MH RX A,S 4C TUM unchanged, except when designated by valid ad-
Multiply (Long) NMD RXF A,S,U,E 6C -;"'RM dresses.
Multiply (Short) NME RXF A,S,U,E 7C TUM The instruction-length code normally is 2 or 3; but OR 0 RX C A,S, 56 TRM OR 01 SI C P,A 96 SPR may be 0, in the case of a data address. OR OC SS C P,A D6 TRM
NAME MNEMONIC TYPE EXCEPTIONS CODE NOTE Pack PACK SS P,A F2 TRM
Add A RX C A,S, IF 5A TRM
Read Direct RDD SI Y M,P,A, 85 TRM
Add Decimal AP SS T,C P,A D, DF FA TRM Set Storage Key SSK RRZ M, A,S 08 Add Halfword AH RX C A,S, IF 4A TRM Set System Mask SSM SI M, A 80 TRM
Add Logical AL RX C A,S, 5E TRM Store ST RX P,A,S 50 SPR Add Normalized Store Character STC RX P,A 42 SPR (Long) NAD RXF,C A,S,U,E,LS 6A TRM Store Halfword STH RX P,A,S 40 SPR Add Normalized Store (Long) STD RXF P,A,S 60 SPR ( Short) NAE RXF,C A,S,U,E,LS 7A TRM Store Multiple STM RS P,A,S 90 TRM
Add Unnorm- Store (Short) STE RXF P,A,S 70 SPR alized (Long) AW RXF,C A,S, E,LS 6E TRM Subtract S RX C A,S, IF 5B TRM
Add Unnorm-Subtract Decimal SP SS T,C P,A, D, DF FB TRM
alized (Short) AU RXF,C A,S, E,LS 7E TRM Subtract
AND N RX C A,S, 54 TRM Halfword SH RX C A,S, IF 4B TRM
Appendix G 149
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