Programming Note
It is possible to modify an instruction in storage by
means of the immediately preceding instructions.
Sequenticd Operation Exceptions
Exceptional instruction addresses or operation codes
cause a program interruption.vVhen the interruption
occurs, the current psw is stored as an oldPSW, and a
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. (In this
manual, part of the description of each class of instruc
tions is a list of the program interruptions that may
occur for these instructions.) The following program
interruptions may occur in normal instruction sequenc
ing, independently of the instruction performed.
Operation: The operation code is not assigned.
Addressing: An instruction halfword is located out
side the available storage for the particular installation.
Specification: The low-order bit of the instruction
addressis one.
In each case, the operation is suppressed; therefore,
the condition code and data in storage and registers
remain unchanged. The instruction address stored as
part of the old psw has been updated by the number
of halfwords indicated by the instruction length code
in the old psw.
Programming Notes
An unavailable instruction address may occur when
normal instruction sequencing proceeds from a valid
storage region into an unavailable region or following
a branching or status-switching operation.
The oeld instruction address can occur only follow
ing branching or status-switching operations.
When the last location in available storage contains
an instruction that again introduces a valid instruction
address,no program interruption is caused, even
though the updated instruction address designates an
unavailable location.
The main-storage or register address specification of
an instruction with unassigned operation code may
cause an addressing or specification interruption when
the requirements for the particular instruction class are
not met.Decisiol1l-Making Branching may be conditional or unconditional. Un conditional branches replace the updated instruction
address with the branch address. Conditional branches
may use the branch address or may leave the updated
instruction address unchanged. When branching takes
place, the instruction is called successful; otherwise, it
is called unsuccessful.
62
Whether a conditional branch is successful depends
on the result of operations concurrent with the branch
or preceding the branch. The former case is repre
sented byBRANCH ON COUNT and the branch-on-index
instructions. The latter case is represented byBRANCH ON CONDITION, which inspects the condition code that reflects the result of a previous arithmetic, logical, or I/O operation.
The condition code provides a means for data-de
pendent decision-making. The code is inspected to
qualify the execution of the conditional-branch instruc
tions. The code is set by some operations to reHect the
result of the operation, independently of the previous
setting of the code. The code remains unchanged for
all other operations.
The condition code occupies bit positions 34 and 35
of the psw. When the psw is stored during status
switching, the condition code is preserved as part of
the psw. Similarly, the condition code is stored as part
of the rightmost half of the psw in a branch-and-link
operation. A new condition code is obtained by aLOAD PSW or SET PROGRAM MASK or by the new psw loaded
as a result of an interruption.
The condition code indicates the outcome of some
of the arithmetic, logical, orI/O operations. It is not
changed for any branching operation, except for EXECUTE. In the case of EXECUTE, the condition code is set
or left unchanged by the subject instruction, as would
have been the case had the subject instruction been in
the normal instruction stream.
The table at the end of this section lists all instruc
tions capable of altering the condition code and the
meaning of the codes for these instructions.
Instruction Formats
Branching instructions use the following three formats:
RR Format
7 8 11 12 15
RX FormatI Op Code I Rl/Mll
X
2
B20 7 8 11 12 1516 1920 31
RS FormatOp Code Rl R3 B2
7 8 11 12 15161920 31
It is possible to modify an instruction in storage by
means of the immediately preceding instructions.
Sequenticd Operation Exceptions
Exceptional instruction addresses or operation codes
cause a program interruption.
occurs, the current psw is stored as an old
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. (In this
manual, part of the description of each class of instruc
tions is a list of the program interruptions that may
occur for these instructions.) The following program
interruptions may occur in normal instruction sequenc
ing, independently of the instruction performed.
Operation: The operation code is not assigned.
Addressing: An instruction halfword is located out
side the available storage for the particular installation.
Specification: The low-order bit of the instruction
address
In each case, the operation is suppressed; therefore,
the condition code and data in storage and registers
remain unchanged. The instruction address stored as
part of the old psw has been updated by the number
of halfwords indicated by the instruction length code
in the old psw.
Programming Notes
An unavailable instruction address may occur when
normal instruction sequencing proceeds from a valid
storage region into an unavailable region or following
a branching or status-switching operation.
The oeld instruction address can occur only follow
ing branching or status-switching operations.
When the last location in available storage contains
an instruction that again introduces a valid instruction
address,
though the updated instruction address designates an
unavailable location.
The main-storage or register address specification of
an instruction with unassigned operation code may
cause an addressing or specification interruption when
the requirements for the particular instruction class are
not met.
address with the branch address. Conditional branches
may use the branch address or may leave the updated
instruction address unchanged. When branching takes
place, the instruction is called successful; otherwise, it
is called unsuccessful.
62
Whether a conditional branch is successful depends
on the result of operations concurrent with the branch
or preceding the branch. The former case is repre
sented by
instructions. The latter case is represented by
The condition code provides a means for data-de
pendent decision-making. The code is inspected to
qualify the execution of the conditional-branch instruc
tions. The code is set by some operations to reHect the
result of the operation, independently of the previous
setting of the code. The code remains unchanged for
all other operations.
The condition code occupies bit positions 34 and 35
of the psw. When the psw is stored during status
switching, the condition code is preserved as part of
the psw. Similarly, the condition code is stored as part
of the rightmost half of the psw in a branch-and-link
operation. A new condition code is obtained by a
as a result of an interruption.
The condition code indicates the outcome of some
of the arithmetic, logical, or
changed for any branching operation, except for EXE
or left unchanged by the subject instruction, as would
have been the case had the subject instruction been in
the normal instruction stream.
The table at the end of this section lists all instruc
tions capable of altering the condition code and the
meaning of the codes for these instructions.
Instruction Formats
Branching instructions use the following three formats:
RR Format
7 8 11 12 15
RX Format
X
2
B2
RS Format
7 8 11 12 1516