Programming Note
It is possible to modify an instruction in storage by
means of the immediately preceding instructions.
Sequenticd Operation Exceptions
Exceptional instruction addresses or operation codes
cause a program interruption. vVhen the interruption
occurs, the current psw is stored as an old PSW, and a
new psw is obtained. The interruption code in the old
psw identifies the cause of the interruption. (In this
manual, part of the description of each class of instruc­
tions is a list of the program interruptions that may
occur for these instructions.) The following program
interruptions may occur in normal instruction sequenc­
ing, independently of the instruction performed.
Operation: The operation code is not assigned.
Addressing: An instruction halfword is located out­
side the available storage for the particular installation.
Specification: The low-order bit of the instruction
address is one.
In each case, the operation is suppressed; therefore,
the condition code and data in storage and registers
remain unchanged. The instruction address stored as
part of the old psw has been updated by the number
of halfwords indicated by the instruction length code
in the old psw.
Programming Notes
An unavailable instruction address may occur when
normal instruction sequencing proceeds from a valid
storage region into an unavailable region or following
a branching or status-switching operation.
The oeld instruction address can occur only follow­
ing branching or status-switching operations.
When the last location in available storage contains
an instruction that again introduces a valid instruction
address, no program interruption is caused, even
though the updated instruction address designates an
unavailable location.
The main-storage or register address specification of
an instruction with unassigned operation code may
cause an addressing or specification interruption when
the requirements for the particular instruction class are
not met. Decisiol1l-Making Branching may be conditional or unconditional. Un­ conditional branches replace the updated instruction
address with the branch address. Conditional branches
may use the branch address or may leave the updated
instruction address unchanged. When branching takes
place, the instruction is called successful; otherwise, it
is called unsuccessful.
Whether a conditional branch is successful depends
on the result of operations concurrent with the branch
or preceding the branch. The former case is repre­
sented by BRANCH ON COUNT and the branch-on-index
instructions. The latter case is represented by BRANCH ON CONDITION, which inspects the condition code that reflects the result of a previous arithmetic, logical, or I/O operation.
The condition code provides a means for data-de­
pendent decision-making. The code is inspected to
qualify the execution of the conditional-branch instruc­
tions. The code is set by some operations to reHect the
result of the operation, independently of the previous
setting of the code. The code remains unchanged for
all other operations.
The condition code occupies bit positions 34 and 35
of the psw. When the psw is stored during status­
switching, the condition code is preserved as part of
the psw. Similarly, the condition code is stored as part
of the rightmost half of the psw in a branch-and-link
operation. A new condition code is obtained by a LOAD PSW or SET PROGRAM MASK or by the new psw loaded
as a result of an interruption.
The condition code indicates the outcome of some
of the arithmetic, logical, or I/O operations. It is not
changed for any branching operation, except for EXE­ CUTE. In the case of EXECUTE, the condition code is set
or left unchanged by the subject instruction, as would
have been the case had the subject instruction been in
the normal instruction stream.
The table at the end of this section lists all instruc­
tions capable of altering the condition code and the
meaning of the codes for these instructions.
Instruction Formats
Branching instructions use the following three formats:
RR Format
7 8 11 12 15
RX Format I Op Code I Rl/Mll
B2 0 7 8 11 12 1516 1920 31
RS Format Op Code Rl R3 B2
7 8 11 12 1516 1920 31
In these formats Rl specifies the address of a gen­
eral register. In BRANCH ON CONDITION a mask field
( M1) identifies the bit values of the condition code.
The branch address is defined differently for the three
In the RR format, the R2 field specifies the address of
a general register containing the branch address, ex­
cept when R2 is zero, which indicates no branching.
The same register may be specified by Rl and R2.
In the RX format, the contents of the general reg­
isters specified by the X2 and B2 fields are added to
the content of the D2 field to form the branch address.
In the RS format, the content of the general register
specified by the B2 field is added to the content of the
D2 field to form the branch address. The Rg field in
this format specifies the location of the second operand
and implies the location of the third operand. The first operand is specified by the Rl field. The third operand
location is always odd. If the Rg field specifies an even
register, the third operand is obtained from the next
higher addressed register. If the Rg field specifies an
odd register, the third operand location coincides with
the second operand location.
A zero in a B2 or X2 field indicates the absence of
the corresponding address component.
An instruction can specify the same general register
for both address modification and operand location.
The order in which the contents of the general reg­
isters are used for the different parts of an operation
1. Address computation.
2. Arithmetic or link information storage.
3. Replacement of the instruction address by the
branch address obtained under step 1.
Results are placed in the general register specified
by R1. Except for the storing of the final results, the
contents of all general registers and storage locations
participating in the addressing or execution part of an
operation remain unchanged.
Programming Note
In several instructions the branch address may be
specified in two ways: in the RX format, the branch
address is the address specified by X2, B2, and D2, in
the RR format, the branch address is the contents of
the register specified by R2. Note that the relation of
the two formats in branch-address specification is not
the same as in operand-address specification. For op­
erands, the address specified by X2, B2, and D2 is the
operand address, but the register specified by R2 con­
tains the operand itself.
Branching Instructions
The branching instructions and their mnemonics, for­
mats, and operation codes follow. The table also shows
which instructions are not part of the small binary in­
struction set and the exceptions that cause a program
interruption. The subject instruction of EXECUTE fol­
lows its own rules for interruptions. The condition
code is never changed for branching instructions.
Branch on
Branch on
Branch and Link
Branch and Link
Branch on Count Branch on Count Branch on Index
Branch on Index
Low or Equal
EX RX A,S, EX 44
A Addressing exception
EX Execute exception S Specification exception
Branch On Condition BCR RR I 07 78 1112 15
7 8 11 12 15 16 19 20 31
The updated instruction address is replaced by the
branch address if the state of the condition code is as
specified by M
; otherwise, normal instruction se­
quencing proceeds with the updated instruction ad­
The Ml field is used as a four-bit mask. The four bits
of the mask correspond, left to right, with the four
condition codes (0, 1, 2, and 3) as follows: CONDITION CODE o
9 10 11
The branch is successful whenever the condition
code has a corresponding mask bit of one.
Condition Code: The code remains unchanged.
Program Interruptions: None.
Branching 63
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