status-modifier bits, with zeros in the other csw fields.
The interruption condition in the device and in the
subchannel is not cleared. On some types of devices, such as the 2702 Trans­
mission Control, the device never provides its current
status in response to TEST I/O, and an interruption
condition can be cleared only by permitting an I/O interruption. When TEST I/O is issued to such a device,
the unit-status field contains the status-modifier bit.
The interruption condition in the device and in the
subchannel, if any, is not cleared.
However, at the time the channel assigns the high­
est priority for interruptions to a condition associated
with an operation at the subchannel, the channel ac­
cepts the status from the device and clears the cor­
responding condition at the device. When TEST I/O is addressed to a device for which the channel has
already accepted the interruption condition, the de­
vice is not selected, and the condition in the subchan­
nel is cleared regardless of the type of device and its
present state. The csw contains unit status and other
information associated with the interruption condi­
tion.
Resulting Condition Code:
o Available
1 csw stored
2 Channel or subchannel busy
3 Not operational
Program Interruptions: Privileged operation.
Programming Notes
Masking of channels provides the program a means of
controlling the priority of I/O interruptions selectively
by channels. The priority of devices attached on a
channel is fixed and cannot be controlled by the pro­
gram. The instruction TEST I/O permits the program to
clear interruption conditions selectively by I/O device.
When a csw is stored by TEST I/O, the interface­
control-check and channel-control-check indications
may be due to a condition already existing in the
channel or due to a condition created by TEST I/O. Similarly, presence of the unit-check bit in the ab­
sence of channel-end, control-unit-end or device-end
bits may be due to either a condition created by the
preceding operation or an equipment error detected
during the execution of TEST I/O. Halt I/O HIO 51
9E 78 1516 1920 31
Execution of the current I/O operation at the address­
ed sub channel or channel is terminated. The subse-
94
quent state of the subchannel depends on the type of
channel. The csw may be stored. The instruction HALT I/O is executed only when the CPU is in the supervisor
state.
Bit positions 21-31 of the sum formed by the addi­
tion of the content of register Bl and the content of
the Dl field identify the I/O device to whose subchan­
nel or channel the instruction applies.
When HALT I/O is issued to a channel operating in
the burst mode, data transfer for the burst operation
is terminated and the device performing the burst
operation is immediately disconnected from the chan­
nel. The subchannel and I/O device address in the in­
struction is ignored. When the instruction is issued to
the multiplexor channel operating in the multiplex
mode and the addressed subchannel is working, data
transfer for the current operation on the subchannel
is terminated. In this case the channel uses the device
address appearing in the instruction to identify the
subchanncl and select the device on the I/O interface.
The address of the device on the subchannel is not
significant, providing the control unit responds to the
address.
The termination of an operation by HALT I/O on the
selector channel causes the channel and su bchannel to
be placed in the interruption-pending state. The in­
terruption condition is generated without receiving
the channel-end signal from the device. When HALT I/O causes an operation on the multiplexor channel to
be terminated, the subchannel remains in the working
state until the device provides the next status byte,
whereupon the subchannel is placed in the interrup­
tion-pending state.
The control unit associated with the terminated
operation remains unavailable for a new I/O operation
until the data-handling portion of the operation in
the control unit is terminated, whereupon it generates
the channel-end condition. Channel end may be gen­
erated at the normal time for the operation, earlier,
or later, depending upon the operation and type of
device. The I/O device executing the terminated oper­
ation remains in ,the working state until termination
of the inherent cycle of the operation, at which time
device end is generated. If blocks of data at the de­
vice are defined, such as reading on magnetic tape,
the recording medium is advanced to the beginning of
the next block.
If the control unit is shared, all devices attached to
the control unit appear in the working state until the
channel-end condition is accepted by the CPU. The
states of the other devices, however, are not perma­
nently affected. Operations such as rewinding mag­
netic tape or positioning a disk access mechanism are

not interrupted, and any pending attention and de­
vice-end conditions in these devices are not reset.
When any of the following conditions occurs, HALT I/O causes the status portion, bit positions 32-47, of
the csw at location 64 to be replaced by a new set of
status bits. The status bits pertain to the device ad­
dressed by instruction. The contents of the other fields
of the csw at location 64 are not changed. The extent
of data transfer and the conditions of termination of
the operation at the subchannel are provided in the
csw associated with the termination.
1. The device on the addressed subchannel current­
ly involved in data transfer in the multiplex mode has
been signaled to terminate the operation. The csw
contains z,eros in the status field.
2. The addressed subchannel on the multiplexor
channel is working, and no burst operation is in prog­
ress, but the control unit or the I/O device is executing
a type of operation or is in such a state that it cannot
accept the halt-I/o signaI. The device has not been
signaled to terminate the operation, but the subchan­
nel has been set up to signal termination to the device
the next time the device requests or offers a byte of
data. The csw unit-status field contains the busy and
status-modifier bits. The channel-status field contains
zeros.
3. The channel detected an equipment malfunction
during the execution of HALT I/O. The status bits in
the csw identify the error condition. The state of the
channel and the progress of the I/O operation are un­
predictable.
When the subchannel on the multiplexor channel is
shared and no burst operation is in progress, HALT I/O causes the operation to be terminated as long as the
instruction is addressed to a device on the currently
working control unit. If another device is addressed, a
malfunction has occurred, or the operator has changed
the state of the operating control unit, no device may
recognize the address. If the device appears not oper­
ational during execution of HALT I/O, condition code
3 is set, and the subchannel is set up to signal ter­
mination to the device the next time the device offers
or requests a byte of data.
Resulting Condition Code:
o Channel and subchannel not working
1 csw stored
2 Burst operation terminated
3 Not operational Program Interruptions: Privileged operation.
Programming Note
The instruction HALT I/O provides the program a
means of terminating an I/O operation before all data
specified in the operation have been transferred. It
permits the program to immediately free the selector
channel for an operation of higher priority. On the
multiplexor channel, HALT I/O provides a means of
controlling real-time operations and permits the pro­
gram to terminate data transmission on a communi­
cation line.
Test Channel TCH 51 9F 78 1516 1920 31
The condition code in the psw is set to indicate the
state of the addressed channeI. The state of the chan­
nel is not affected, and no action is caused. The in­
struction TEST CHANNEL is executed only when the CPU is in the supervisor state.
Bit positions 21-23 of the sum formed by the addi­
tion of the content of register Bl and the content of
the Dl field identify the channel to which the instruc­
tion applies. Bit positions 24-31 of the address are
ignored.
The instruction TEST CHANNEL inspects only the state
of the addressed channeI. It tests whether the channel
is operating in the burst mode, is aware of any out­
standing interruption conditions from its devices, or
is not operationaI. When none of these conditions
exists, the available state is indicated. No device is
selected, and, on the multiplexor channel, the sub­
channels are not interrogated.
Resulting Condition Code:
o Channel available
1 Interruption pending in channel
2 Channel operating in burst mode
3 Channel not operational
Input/Output Operations 95