The contents of bit positions 8-15 of the SUPERVISOR CALL become bits 24-31 in the interruption code of the
old psw. Bits 16-23 of the interruption code are made
zero. The instruction-length code is 1, indicating the
halfword length of SUPERVISOR CALL. Programming Notes
The name "supervisor call" indicates that one of the
major purposes of the interruption is the switching
from problem to supervisor state. This major purpose
does not preclude the use of this interruption for other
types of status-switching.
The jnterruption code may be used to convey a
message from the calling program to the supervisor.
When SUPERVISOR CALL is performed as the subject
instruction of EXECUTE, the instruction-length code is 2.
External Interruption
The external interruption provides a means by which
the CPU responds to signals from the timer, from the
interrupt key, and from external units.
A request for an external interruption may occur at
any time, and requests from diHerent sources may
occur at the same time. Requests are preserved until
honored by the CPU. All pending requests are pre­
sented simultaneously when an external interruption
occurs. Each request is presented only once. When
several requests from one source are made before the
interruption is taken, only one interruption occurs.
An external interruption can occur only when sys­
tem mask bit 7 is one and after execution of the cur­
rent instruction is completed. The interruption causes
the old psw to be stored at location 24 and a new
psw to be fetched from location 88.
The source of the interruption is identified by inter­
ruption-code bits 24-31. The remainder of the interrup­
tion code, psw bits 16-23, is made zero. The instruc­
tion-length code is unpredictable for external inter­
A timer value changing from positive to negative
causes an external interruption with bit 24 of the in­
terruption code turned on.
Timer 111111111 23 24 25 26 27 28 29 30 31
The timer occupies a 32-bit word at storage location
80. In the standard form, the contents of the timer are
reduced by a one in bit position 21 and in bit position 80 23 every 1/60th of a second or the timer contents are
reduced by one in bit position 21 and in bit position 22
every 1/50th of a second. The choice is determined by
the available line frequency. The gross result in either
case is equivalent to reducing the timer by one in bit
position 23 every 1/300th of a second.
Higher resolution may be obtained in some models
by counting with higher frequency in one of the posi­
tions 24 through 31. In each case, the frequency is ad­
justed to give counting at 300 cycles per second in bit
23, as shown in the table. The full cycle of the timer
is 15.5 hours.
24 600 cps 1.67 ms
25 1.2 kc 833 fLS 26 2.4 kc 417 fLS 27 4.8 kc 208 fLS 28 9.6 kc 104 fLS 29 19.2 kc 52 fLS 30 38.4 kc 26 fLS 31 76.8 kc . 13 fLS The count is treated as a signed integer by following
the rules for fixed-pOint arithmetic. The negative over­
flow, occurring as the timer is counted from a large
negative number to a large positive number, is ig­
nored. The interruption is initiated as the count pro­
ceeds from a positive number, including zero, to a
negative number.
The timer is updated whenever access to storage
permits. An updated timer value is normally available
at the end of each instruction execution; thus, a real­
time count can be maintained. Timer updating may he
omitted when I/O data transmission approaches the
limit of storage capability and when the instruction
time for READ DIRECT is excessive.
After an interruption is initiated, the timer may
have been updated several times before the CPU is
actually interrupted, depending upon instruction exe­
cution time.
The timer remains unchanged when the CPU is in
the stopped state or when the rate switch on the
operator intervention panel is set to INSTRUCTION STEP. The timer value may be changed at any time by
storing a new value in storage location 80 (except
when this location is protected).
The timer is an optional feature on some models.
Programming Note
The timer in association with a program can serve both
as a real-time clock and as an interval timer. Interrupt Key
Pressing the interrupt key on the operator control
section of the system control panel causes an external
interruption with bit 25 of the interruption code
turned on.
The key is active while power is on. External Signal An external signal causes an external interruption,
with the corresponding bit in the interruption code
turned on.
A total of six signal-in lines may be connected to
the CPU for receiving external signals. The pattern
presented in interruption-code bits 26-31 depends
upon the pattern received before the interruption is
The external signals are part of the direct control
Programming Note
The signal-in lines of one CPU may be connected to the
signal-out timing lines of the direct control feature or
the machine check out-line of the multisystem feature
of another CPU. An interconnection of this kind allows
one CPU to interrupt another. Also, the direct-out lines
of one CPU may be connected to the direct-in lincs of
the other, and vice versa.
Machine-Check Interruption
The machine-check interruption provides a means for
recovery from and fault location of machine malfunc­
When the machine-check mask bit is one, occur­
rence of a machine check terminates the current in­
struction, initiates a diagnostic procedure, issues a
signal on the machine check out-line, and subsequent­
ly causes the machine-check interruption.
The old psw is stored at location 48 with an inter­
ruption code of zero. The state of the CPU is scanned
out into the storage area, starting with location 128
and extending through as many words as the given CPU requires. The new psw is fetched from location
112. Proper execution of these steps depends on the
nature of the machine check.
The machine check out-signal is provided as part of
the multisystem feature. The signal is a O.5-micro­
second to l.O-mierosecond timing signal that follows
the I/O interface line-driving and terminating specifi­
cations. The signal is designed so that it has a high
probability of being issued in the presence of machine
When the machine-check mask bit is zero, an at­
tempt is made to complete the current instruction
upon the occurrence of a machine check and to pro­
ceed with the next sequential instruction. No diagnos­
tic procedure, signal, or interruption occurs.
A change in the machine-check mask bit due to the
loading of a new psw results in a change in the treat­
ment of machine checks. Depending on the nature of
a machine check, the earlier treatment may still be in
force for several cycles.
Following emergency power turn-off and turn-on
or system reset, incorrect parity may exist in storage
or registers. Unless new information is loaded, a ma­
chine check may occur erroneously. Once storage and
registers are cleared, a machine check can be caused
only by machine malfunction and never by data or in­
Machine checks occurring in operations executed
by I/O channels either cause a machine-check inter­
ruption or are recorded in the channel status word for
that operation.
Priority of Interruptions
During execution of an instruction, several interrup­
tion-causing events may occur simultaneously. The
instruction may give rise to a program interruption, an
external interruption may occur, a machine check may
occur, and an I/O interruption request may be made.
Instead of the program interruption, a supervisor-call might occur; however, both cannot occur
since these two interruptions are mutually exclusive.
Simu1taneous interruption requests are honored in a
predetermined order.
The machine-check interruption has highest priority.
When it occurs, the current operation is terminated.
Program and supervisor-call interruptions that would
have occurred as a result of the current instruction are
eliminated. Every reasonable attempt is made to limit
the side-effects of a machine check. Normally, I/O and
external interruptions, as well as the progress of the I/O data transfer and the updating of the timer, re­
main unaffected.
When no machine check occurs, the program inter­
ruption or supervisor-call interruption is taken first, the
external interruption is taken next, and the I/O inter­
ruption is taken last. The action consists of storing the
old psw and fetching the new psw belonging to the
interruption first taken. This new psw is subsequently
stored without any instruction execution, and the next
interruption psw is fetched. This storing and fetching
continues until no more interruptions are to be serv­
iced. The external and I/O interruptions are taken only
if the immediately preceding psw indicates that the CPU is interruptable for these causes.
Instruction execution is resumed using the last­
fetched psw. The order of executing interruption sub­
routines is therefore the reverse of the order in which
the psw's arc fetched.
Interruptions 81
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